Verilog Interiew Quetions Collection : What is the difference between $display and $monitor and $write and $strobe? What is the difference between code-compiled simulator and normal simulator? What is the difference between wire and reg? What is the
Verilog 常见错误汇总 1.Found clock-sensitive change during active clock edge at time <time> on register "<name>" 原因:vector source file中时钟敏感信号(如:数据,允许端,清零,同步加载等)在时钟的边缘同时变化.而时钟敏感信号是不能在时钟边沿变化的.其后果为导致结果不正确. 措施:编辑vector source file 2.Verilog HD