spi slaver接口的fpga实现
2024-10-14 20:32:20
前言
spi从机接口程序，数据位8bit，sck空闲时低电平，工作时第一个沿数据传输。只有一个从机，cs低电平片选，slaver开始工作。
流程：
接口定义：
编码实现：（版权所有，请勿用于商业用途，仅供学习使用）
//************************************************
// Filename : spi_sm.v
// Author : Kingstacker
// Company : School
// Email : kingstacker_work@163.com
// Device : Altera cyclone4 ep4ce6f17c8
// Description : spi slaver module,mode is 0 ;data 8bit;
//************************************************
module spi_sm #(parameter WIDTH = )(
//input;
input wire clk,
input wire rst_n,
input wire cs, //slave select;
input wire sck, //data exchange clock;
input wire [WIDTH-:] slaver_din, //the data you want send;
input wire mosi, //the data form master;
//output;
output reg miso, //slaver out;
output reg [WIDTH-:] slaver_dout //the data you received;
);
localparam MISO_CNT_MAX = 'd7;
reg cs_reg1;
reg cs_reg2;
reg sck_reg1;
reg sck_reg2;
wire cs_p; //posedge cs;
wire cs_n; //negedge cs;
wire sck_p; //posedge sck;
wire sck_n; //negedge sck;
reg [WIDTH-:] slaver_din_reg;
reg [WIDTH-:] slaver_dout_reg;
reg [:] miso_cnt;
//produce cs_p and cs_n;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
cs_reg1 <= 'b0;
cs_reg2 <= 'b0;
end //if
else begin
cs_reg1 <= cs;
cs_reg2 <= cs_reg1;
end //else
end //always
assign cs_p = (cs_reg1 & (~cs_reg2)); //cs posedge;
assign cs_n = ((~cs_reg1) & cs_reg2); //cs negedge;
//produce sck_p and sck_n;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
sck_reg1 <= 'b0;
sck_reg2 <= 'b0;
end //if
else begin
sck_reg1 <= sck;
sck_reg2 <= sck_reg1;
end //else
end //always
assign sck_p = (sck_reg1 & (~sck_reg2)); //sck posedge;
assign sck_n = ((~sck_reg1) & sck_reg2); //sck negedge;
//you want send data registed;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
slaver_din_reg <= ;
end //if
else begin
slaver_din_reg <= (cs_n) ? slaver_din :slaver_din_reg;
end //else
end //always
//recieved data ;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
slaver_dout <= ;
end //if
else begin
slaver_dout <= (cs_p) ? slaver_dout_reg : slaver_dout;
end //else
end //always
//sck negedge sample mosi;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
slaver_dout_reg <= ;
end //if
else begin
slaver_dout_reg <= (sck_n) ? {slaver_dout_reg[:],mosi} : slaver_dout_reg;
end //else
end //always
//miso cnt;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
miso_cnt <= ;
end
else begin
if (sck_p) begin
if (miso_cnt == MISO_CNT_MAX) begin
miso_cnt <= ;
end
else begin
miso_cnt <= miso_cnt + 'b1;
end
end
else begin
miso_cnt <= miso_cnt;
end
end
end
//sck posedge output the miso;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
miso <= ;
end //if
else begin
miso <= (sck_p) ? slaver_din_reg[MISO_CNT_MAX-miso_cnt] : miso;
end //else
end //always endmodule
以上。
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