VHDL之concurrent之generate

GENERATE

　　It is another concurrent statement (along with operators and WHEN). It is equivalent to the sequential statement LOOP in the sense that it

allows a section of code to be repeated a number of times, thus creating several instances of the same assignments.

　　1)　　FOR / GENERATE:　notice that GENERATE must be labeled.

label: FOR identifier IN range GENERATE

　　(concurrent assignments)

END GENERATE;

　　2)　　IF/GENERATE

　　An irregular form is also available, which uses IF/GENERATE (with an IF equivalent; recall that originally IF is a sequential statement). Here ELSE is not allowed.　　

label1: FOR identifier IN range GENERATE

　　...

label2: IF condition GENERATE

　　(concurrent assignments)

END GENERATE;

...

END GENERATE;

Example 1

SIGNAL x: BIT_VECTOR ( DOWNTO );

SIGNAL y: BIT_VECTOR ( DOWNTO );

SIGNAL z: BIT_VECTOR ( DOWNTO );

...

G1: FOR i IN x'RANGE GENERATE

　　z(i) <= x(i) AND y(i+);

END GENERATE;

Example 2 Vector Shifter

　　The output vector must be a shifted version of the input vector, with twice its width and an amount of shift speciﬁed by another input.

For example, if the input bus has width 4, and the present value is ‘‘1111’’, then the output should be one of the lines of the following

matrix (the original vector is underscored):

　　row(0): 0 0 0 0 1 1 1 1

　　row(1): 0 0 0 1 1 1 1 0

　　row(2): 0 0 1 1 1 1 0 0

　　row(3): 0 1 1 1 1 0 0 0

　　row(4): 1 1 1 1 0 0 0 0

 ------------------------------------------------

 LIBRARY ieee;

 USE ieee.std_logic_1164.all;

 ------------------------------------------------

 ENTITY shifter IS

 PORT ( inp: IN STD_LOGIC_VECTOR ( DOWNTO );

 　　　　sel: IN INTEGER RANGE  TO ;

 　　　　outp: OUT STD_LOGIC_VECTOR ( DOWNTO ));

 END shifter;

 ------------------------------------------------

 ARCHITECTURE shifter OF shifter IS

 　　SUBTYPE vector IS STD_LOGIC_VECTOR ( DOWNTO );

 　　TYPE matrix IS ARRAY ( DOWNTO ) OF vector;

 　　SIGNAL row: matrix;

 BEGIN

 　　row() <= "" & inp;

 　　G1: FOR i IN  TO  GENERATE

 　　　　row(i) <= row(i-)( DOWNTO ) & '';

 　　END GENERATE;

 　　outp <= row(sel);

 END shifter;

 ------------------------------------------------

巴特西

VHDL之concurrent之generate

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