FPGA MIG调试bug（二）

目标器件：复旦微FPGA：JFM7K325T8FCBGA676（对标Xilinx Kintex-7系的XC7K325T）

工程背景：送入FPGA的外部时钟为差分时钟，时钟送入FPGA后，经过PLL输出至DDR3，但在implementation时失败

bug message：

[Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_wiz_0_inst/inst/clk_in1_clk_wiz_0] >

clk_wiz_0_inst/inst/clkin1_ibufgds (IBUFDS.O) is locked to IOB_X1Y72
clk_wiz_0_inst/inst/plle2_adv_inst (PLLE2_ADV.CLKIN1) is provisionally placed by clockplacer on PLLE2_ADV_X1Y0

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_pll_bufg
Status: PASS
Rule Description: A PLL driving a BUFG must be placed on the same half side (top/bottom) of the device
clk_wiz_0_inst/inst/plle2_adv_inst (PLLE2_ADV.CLKFBOUT) is provisionally placed by clockplacer on PLLE2_ADV_X1Y0
and clk_wiz_0_inst/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

原因分析：

The IO port and PLL are not in same clock region hence you are seeing the error.

解决办法：

将IO Ports送入的时钟信号通过IBUFG，然后送入PLL，即可解决，本工程中因为采用的差分时钟输入，所以原语选用IBUFGDS，生成的单端时钟送入PLL，PLL的时钟source选择 Global buffer，解决

巴特西

FPGA MIG调试bug（二）

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