//------------------------------------------------------------------------------

// TITLE: Register Sequence Classes

//------------------------------------------------------------------------------

//

// This section defines the base classes used for register stimulus generation.

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

//

// CLASS: uvm_reg_sequence

//

// This class provides base functionality for both user-defined RegModel test

// sequences and "register translation sequences".

//

// - When used as a base for user-defined RegModel test sequences, this class

//   provides convenience methods for reading and writing registers and

//   memories. Users implement the body() method to interact directly with

//   the RegModel model (held in the <model> property) or indirectly via the

//   delegation methods in this class.

//

// - When used as a translation sequence, objects of this class are

//   executed directly on a bus sequencer which are used in support of a layered sequencer

//   use model, a pre-defined convert-and-execute algorithm is provided.

//

// Register operations do not require extending this class if none of the above

// services are needed. Register test sequences can be extend from the base

// <uvm_sequence #(REQ,RSP)> base class or even from outside a sequence.

//

// Note- The convenience API not yet implemented.

//------------------------------------------------------------------------------

class uvm_reg_sequence #(type BASE=uvm_sequence #(uvm_reg_item)) extends BASE;

  `uvm_object_param_utils(uvm_reg_sequence #(BASE))

  // Parameter: BASE

  //

  // Specifies the sequence type to extend from.

  //

  // When used as a translation sequence running on a bus sequencer, ~BASE~ must

  // be compatible with the sequence type expected by the bus sequencer.

  //

  // When used as a test sequence running on a particular sequencer, ~BASE~

  // must be compatible with the sequence type expected by that sequencer.

  //

  // When used as a virtual test sequence without a sequencer, ~BASE~ does

  // not need to be specified, i.e. the default specialization is adequate.

  //

  // To maximize opportunities for reuse, user-defined RegModel sequences should

  // "promote" the BASE parameter.

  //

  // | class my_reg_sequence #(type BASE=uvm_sequence #(uvm_reg_item))

  // |                               extends uvm_reg_sequence #(BASE);

  //

  // This way, the RegModel sequence can be extended from

  // user-defined base sequences.

  // Variable: model

  //

  // Block abstraction this sequence executes on, defined only when this

  // sequence is a user-defined test sequence.

  //

  uvm_reg_block model;

  // Variable: adapter

  //

  // Adapter to use for translating between abstract register transactions

  // and physical bus transactions, defined only when this sequence is a

  // translation sequence.

  //

  uvm_reg_adapter adapter;

  // Variable: reg_seqr

  //

  // Layered upstream "register" sequencer.

  //

  // Specifies the upstream sequencer between abstract register transactions

  // and physical bus transactions. Defined only when this sequence is a

  // translation sequence, and we want to "pull" from an upstream sequencer.

  //

  uvm_sequencer #(uvm_reg_item) reg_seqr;

//------------------------------------------------------------------------------

// Class: uvm_reg_frontdoor

//

// Facade class for register and memory frontdoor access.

//------------------------------------------------------------------------------

//

// User-defined frontdoor access sequence

//

// Base class for user-defined access to register and memory reads and writes

// through a physical interface.

//

// By default, different registers and memories are mapped to different

// addresses in the address space and are accessed via those exclusively

// through physical addresses.

//

// The frontdoor allows access using a non-linear and/or non-mapped mechanism.

// Users can extend this class to provide the physical access to these registers.

//

virtual class uvm_reg_frontdoor extends uvm_reg_sequence #(uvm_sequence #(uvm_sequence_item));

   // Variable: rw_info

   //

   // Holds information about the register being read or written

   //

   uvm_reg_item rw_info;

   // Variable: sequencer

   //

   // Sequencer executing the operation

   //

   uvm_sequencer_base sequencer;

   // Function: new

   //

   // Constructor, new object given optional ~name~.

   //

   function new(string name="");

      super.new(name);

   endfunction

   string fname;

   int lineno;

endclass: uvm_reg_frontdoor