-- port

 scl_i   : in    std_logic;

 sda_i   : in    std_logic;

 5 -- architecture

 7 -- block

 bus_status_ctrl : block

   singal cSCL, cSDA    : std_logic_vector( downto );

 capture_scl_sda: process(clk, nRst)

 begin

     if (nRst = '') then

         cSCL <= "";

         cSDA <= "";

     elsif (clk'event and clk = '') then

         if (rst = '') then

             cSCL <= "";

             cSDA <= "";

         else

             cSCL <= (cSCL() & scl_i);

             cSDA <= (cSDA() & sda_i);

         endif;

     endif;

 end process capture_scl_sda;

 1 -- port

   ena     : in std_logic;               -- core enable signal

   clk_cnt : in unsigned( downto );   -- clock prescale value

 5 -- block

  signal fSCL  : std_logic_vector( downto ); -- filter inputs for SCL

  signal  fSDA : std_logic_vector( downto ); -- filter inputs for SDA

  signal filter_cnt  : unsigned( downto );  -- clock divider for filter

 filter_divider: process(clk, nRst)

 begin

     if (nRst = '') then

         filter_cnt <= (others => '');

     elsif (clk'event and clk = '') then

         if ( (rst = '') or (ena = '') ) then

             filter_cnt <= (others => '');

         elsif (filter_cnt = ) then

             filter_cnt <= clk_cnt( downto );

         else

             filter_cnt <= filter_cnt -;

         end if;

     end if;

 end process filter_divider;

 filter_scl_sda: process(clk, nRst)

 begin

     if (nRst = '') then

         fSCL <= (others => '');

         fSDA <= (others => '');

     elsif (clk'event and clk = '') then

         if (rst = '') then

             fSCL <= (others => '');

             fSDA <= (others => '');

         elsif (filter_cnt = ) then

             fSCL <= (fSCL( downto ) & cSCL());

             fSDA <= (fSDA( downto ) & cSDA());

         end if;

     end if;

 end process filter_scl_sda;

 1 -- architecture

  signal sSCL, sSDA : std_logic;   -- synchronized SCL and SDA inputs

  signal dSCL, dSDA : std_logic;   -- delayed versions ofsSCL and sSDA

 5 -- block

 scl_sda: process(clk, nRst)

 begin

    if (nRst = '') then

        sSCL <= '';

        sSDA <= '';

        dSCL <= '';

        dSDA <= '';

    elsif (clk'event and clk = '') then

        if (rst = '') then

            sSCL <= '';

            sSDA <= '';

            dSCL <= '';

            dSDA <= '';

        else

           sSCL <= (fSCL() and fSCL()) or

                   (fSCL() and fSCL()) or

                   (fSCL() and fSCL());

           sSDA <= (fSDA() and fSDA()) or

                   (fSDA() and fSDA()) or

                   (fSDA() and fSDA());

           dSCL <= sSCL;

           dSDA <= sSDA;

        end if;

    end if;

 end process scl_sda;