HDLbits——Exams/2014 q4b

题目要求

使用verilog描述如图所示得移位寄存器：

Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.

Connect the R inputs to the SW switches,

clk to KEY[0],

E to KEY[1],

L to KEY[2], and

w to KEY[3].

Connect the outputs to the red lights LEDR[3:0].



// Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.

// Connect the R inputs to the SW switches,

// clk to KEY[0],

// E to KEY[1],

// L to KEY[2], and

// w to KEY[3].

// Connect the outputs to the red lights LEDR[3:0].

module top_module (

    input [3:0] SW,

    input [3:0] KEY,

    output [3:0] LEDR

); //

MUXDFF ins3_MUXDFF(.clk(KEY[0]), .R(SW[3]),.E(KEY[1]),.L(KEY[2]),.w(KEY[3]), .Q(LEDR[3]));

MUXDFF ins2_MUXDFF(.clk(KEY[0]),.R(SW[2]),.E(KEY[1]),.L(KEY[2]),.w(LEDR[3]),.Q(LEDR[2]));

MUXDFF ins1_MUXDFF(.clk(KEY[0]),.R(SW[1]),.E(KEY[1]),.L(KEY[2]),.w(LEDR[2]),.Q(LEDR[1]));

MUXDFF ins0_MUXDFF(.clk(KEY[0]),.R(SW[0]),.E(KEY[1]),.L(KEY[2]),.w(LEDR[1]),.Q(LEDR[0]));

endmodule

module MUXDFF (

    input clk,

    input w, R, E, L,

    output reg Q

);

wire D_i;

assign D_i = L?R:(E?w:Q);

always @(posedge clk) begin

    Q <= D_i;

end

endmodule

RTL原理图

巴特西

HDLbits——Exams/2014 q4b

题目要求

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