HDL代码风格建议（2）乘法器和DSP推断
2024-09-26 16:22:16
Inferring Multipliers and DSP Functions
Inferring Multipliers
module unsigned_mult (out, a, b);
output [:] out;
input [:] a;
input [:] b;
assign out = a * b;
endmodule
Verilog HDL Usigned Multiplier
Note: The signed declaration in Verilog HDL is a feature of the Verilog 2001 Standard.
module signed_mult (out, clk, a, b);
output [:] out;
input clk;
input signed [:] a;
input signed [:] b;
reg signed [:] a_reg;
reg signed [:] b_reg;
reg signed [:] out;
wire signed [:] mult_out;
assign mult_out = a_reg * b_reg;
always @ (posedge clk)
begin
a_reg <= a;
b_reg <= b;
out <= mult_out;
end
endmodule
Verilog HDL Signed Multiplier with Input and Output Regist
Inferring Multiply‑Accumulator and Multiply-Adder
The Verilog HDL and VHDL code samples infer multiply-accumulators and multiply-adders with input, output, and pipeline registers, as well as an optional asynchronous clear signal. Using the three sets of registers provides the best performance through the function, with a latency of three. You can remove the registers in your design to reduce the latency.
module unsig_altmult_accum (dataout, dataa, datab, clk, aclr, clken);
input [:] dataa, datab;
input clk, aclr, clken;
output reg[:] dataout;
reg [:] dataa_reg, datab_reg;
reg [:] multa_reg;
wire [:] multa;
wire [:] adder_out;
assign multa = dataa_reg * datab_reg;
assign adder_out = multa_reg + dataout;
always @ (posedge clk or posedge aclr)
begin
if (aclr)
begin
dataa_reg <= 'b0;
datab_reg <= 'b0;
multa_reg <= 'b0;
dataout <= 'b0;
end
else if (clken)
begin
dataa_reg <= dataa;
datab_reg <= datab;
multa_reg <= multa;
dataout <= adder_out;
end
end
endmodule
Verilog HDL Unsigned Multiply-Accumulator
module sig_altmult_add (dataa, datab, datac, datad, clock, aclr, result);
input signed [:] dataa, datab, datac, datad;
input clock, aclr;
output reg signed [:] result;
reg signed [:] dataa_reg, datab_reg, datac_reg, datad_reg;
reg signed [:] mult0_result, mult1_result;
always @ (posedge clock or posedge aclr) begin
if (aclr) begin
dataa_reg <= 'b0;
datab_reg <= 'b0;
datac_reg <= 'b0;
datad_reg <= 'b0;
mult0_result <= 'b0;
mult1_result <= 'b0;
result <= 'b0;
end
else begin
dataa_reg <= dataa;
datab_reg <= datab;
datac_reg <= datac;
datad_reg <= datad;
mult0_result <= dataa_reg * datab_reg;
mult1_result <= datac_reg * datad_reg;
result <= mult0_result + mult1_result;
end
end
endmodule
Verilog HDL Signed Multiply-Adder
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