Allwinner F1C100s coremark测试
2024-09-05 10:07:58
ccu register base:0x01c20000
devmem 0x01c20000
The PLL output=(24MHz*N*K)/(M*P)
N=31
K=1
M=1
P=/1
register value: 0x90001e00
cpu clock=744MHz
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 13405
Total time (secs): 13.405000
Iterations/Sec : 1491.980604
Iterations : 20000
Compiler version : GCC8.4.0
Compiler flags : -O2 -lrt
Memory location : Please put data memory location here
(e.g. code in flash, data on heap etc)
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0x382f
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 1491.980604 / GCC8.4.0 -O2 -lrt / Heap
The PLL output=(24MHz*N*K)/(M*P)
N=32
K=1
M=1
P=/1
register value: 0x90001e00
cpu clock=768MHz
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 12985
Total time (secs): 12.985000
Iterations/Sec : 1540.238737
Iterations : 20000
Compiler version : GCC8.4.0
Compiler flags : -O2 -lrt
Memory location : Please put data memory location here
(e.g. code in flash, data on heap etc)
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0x382f
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 1540.238737 / GCC8.4.0 -O2 -lrt / Heap
结论
在dram频率200MHz下，每MHz频率提升，coremark分数约提升2
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