Linux中使用Makefile来运行QuestaSim

环境：Win7x64，VMware15.0，centOS7.0，QuestaSim10.7c

假设已经编辑好了一个全加器还有运行这个DUT的testbech，代码如下：

点击查看代码

// filename： full_adder.v

module full_adder(

  input wire a_in,

  input wire b_in,

  input wire c_in,

  output wire sum_out,

  output wire c_out

);

assign sum_out = a_in & b_in & c_in;

assign c_out = (a_in & b_in) | (b_in & c_in) | (a_in & c_in);

endmodule

和

点击查看代码

// filename: full_adder_tb.v

module full_adder_tb;

  reg ain, bin, cin;

  wire sumout, cout;

  //task 1: createan instance

  full_adder u_full_adder(

    .a_in (ain),

    .b_in (bin),

    .c_in (cin),

    .sum_out (sumout),

    .c_out (cout)

  );

  //task 2: clock and reset generator

  parameter CLK_PERIOD = 20;

  reg clk, reset_n;

  initial begin

    clk = 0;

    forever begin

      #(CLK_PERIOD/2) clk = ~clk;

    end

  end

  initial begin

    reset_n = 0;

    #100 reset_n = 1;

  end

  //task 3: drive the stimulus and capture the response

  initial begin

    #110 ain = 0; bin = 0; cin =0; //00

    #20 ain = 0; bin = 1; cin =0; //01

    #20 ain = 1; bin = 0; cin =0; //01

    #20 ain = 1; bin = 1; cin =0; //10

    #20 ain = 0; bin = 0; cin =1; //01

    #20 ain = 0; bin = 1; cin =1; //10

    #20 ain = 1; bin = 0; cin =1; //10

    #20 ain = 1; bin = 1; cin =1; //11

    #50 $finish;

  end

  //task 4: check the result

  always @ (posedge clk) begin

    if(!reset_n)begin

      $display("%t:%m:resetting...",$time);

    end

    else begin

      $display("%t:%m:resetting finish!",$time);

    end

  end

  initial begin

    #115 if({cout,sumout}!=2'b00)

      $display("%t, Error: {cout,sumout} = %b, ain = %b, bin = %b, cin = %b", $time, {cout,sumout}, ain, bin, cin);

    #20 if({cout,sumout} != 2'b01)

      $display("Error: {cout,sumout} = %b, ain = %b, bin = %b, cin = %b", {cout,sumout}, ain, bin, cin);

    #20 if({cout,sumout} != 2'b01)

      $display("Error: {cout,sumout} = %b, ain = %b, bin = %b, cin = %b", {cout,sumout}, ain, bin, cin);

    #20 if({cout,sumout} != 2'b10)

      $display("Error: {cout,sumout} = %b, ain = %b, bin = %b, cin = %b", {cout,sumout}, ain, bin, cin);

    #20 if({cout,sumout} != 2'b01)

      $display("Error: {cout,sumout} = %b, ain = %b, bin = %b, cin = %b", {cout,sumout}, ain, bin, cin);

    #20 if({cout,sumout} != 2'b10)

      $display("Error: {cout,sumout} = %b, ain = %b, bin = %b, cin = %b", {cout,sumout}, ain, bin, cin);

    #20 if({cout,sumout} != 2'b10)

      $display("Error: {cout,sumout} = %b, ain = %b, bin = %b, cin = %b", {cout,sumout}, ain, bin, cin);

    #20 if({cout,sumout} != 2'b11)

      $display("Error: {cout,sumout} = %b, ain = %b, bin = %b, cin = %b", {cout,sumout}, ain, bin, cin);

  end

  //task 5: dump wave form with the compile option -debug_all

  initial begin

    $vcdpluson;

  end

endmodule

方法一、运行QuestaSim界面来进行仿真

打开终端

输入：which vsim //查找QuestaSim位置并确认其可用性

输入：vsim 打开软件

balabala：

New Project: Name: full_adder, Default Library Name: work

-> Add existing file: full_adder.v, full_adder_tb.v

-> Compile All

-> Start simulation: work.full_adder_tb.v

-> Object: Add Wave -> Run or Run all

方法二：新建makefile，代码如下，终端输入make即可：

all: create_lib compile simulate 

create_lib:

	vlib work

compile:

	vlog -l comp.log -sv full_adder.v full_adder_tb.v

simulate:

	vsim -l sim.log -voptargs=+acc work.full_adder_tb -do "log -r *; run -all"

clean:

	rm -rf *work mti_lib transcript modelsim.ini *wlf seq.cr.mti seq.mpf *.log

就可以啦。

两个小问题：

1、QuestaSim中代码模块字体显示过小的问题

2、novopt: Optimizations are Disabled的问题

3、$vcdpluson is not defined的问题

4、makefile的代替版本【For VCS】：

点击查看代码

run: compile simulate

compile

	vcs -debug_all timescale.v full_adder.v full_adder_tb.v -l com.log

simulate:

	./simv -l sim.log

run_cov: compile_coverage simulate_coverage

compile_coverage:

	vcs -debug_all -cm line+cond+fsm+tgl+branch -lca timescale.v full_adder.v full_adder_tb.v -l com.log

simulate_coverage:

	./simv -cm line+cond+fsm+tgl+branch -lca -cm_log cm.log -l sim.log

clean:

	rm -rf *.log

Good Luck !

巴特西

Linux中使用Makefile来运行QuestaSim

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