# -----------------------------------------------------------------------------

 # Vivado Non-Project Flow

 # -----------------------------------------------------------------------------

 set DESIGN [lindex $argv ]

 # -----------------------------------------------------------------------------

 config_webtalk -user off

 # -----------------------------------------------------------------------------

 create_project -in_memory

 # -----------------------------------------------------------------------------

 proc read_filelist {filelist} {

     global hdl_list

     global incdir_list

     set fp [open $filelist r]

     while {[gets $fp fname] != -} {

         if {[regexp {^//} $fname]} {

             continue

         } elseif {[regexp {^\S+\.v} $fname]} {

             lappend hdl_list $fname

         } elseif {[regexp {^-v} $fname]} {

             regsub {^-v} $fname "" fname_sub

             lappend hdl_list $fname_sub

         } elseif {[regexp {^\+incdir\+} $fname]} {

             regsub {^\+incdir\+} $fname "" fname_sub

             lappend incdir_list $fname_sub

         }

     }

     close $fp

 }

 # -----------------------------------------------------------------------------

 set hdl_list ""

 set incdir_list ""

 read_filelist "../../rtl/filelist.f"

 set_property verilog_define "SYNTHESIS" [current_fileset]

 set_property include_dirs $incdir_list [current_fileset]

 set_property top ${DESIGN} [current_fileset]

 read_verilog $hdl_list

 #read_ip "../scr/ila_debug.xci"

 read_xdc "../scr/${DESIGN}.xdc"

 # -----------------------------------------------------------------------------

 synth_design -top ${DESIGN} -part xc7z020clg400-

 write_checkpoint -force ../rpt/${DESIGN}_synth.dcp

 report_utilization -file ../rpt/${DESIGN}_synth_utilization.rpt

 report_timing_summary -file ../rpt/${DESIGN}_synth_timing_summary.rpt

 # -----------------------------------------------------------------------------

 if {[llength [get_debug_cores -quiet]] > } {

     implement_debug_core

 }

 write_debug_probes ../rpt/${DESIGN}.ltx

 # -----------------------------------------------------------------------------

 opt_design -directive Explore

 place_design -directive Explore

 phys_opt_design -directive Explore

 write_checkpoint -force ../rpt/${DESIGN}_placed.dcp

 report_utilization -file ../rpt/${DESIGN}_placed_utilization.rpt

 report_timing_summary -file ../rpt/${DESIGN}_placed_timing_summary.rpt

 # -----------------------------------------------------------------------------

 route_design -directive Explore -tns_cleanup

 phys_opt_design -directive Explore

 write_checkpoint -force ../rpt/${DESIGN}_routed.dcp

 report_route_status -file ../rpt/${DESIGN}_routed_status.rpt

 report_timing_summary -file ../rpt/${DESIGN}_routed_timing_summary.rpt

 # -----------------------------------------------------------------------------

 write_bitstream -force ../rpt/${DESIGN}.bit

 write_cfgmem -format bin -interface SPIx1 -size  -loadbit "up 0 ../rpt/${DESIGN}.bit" ../rpt/${DESIGN}.bin