//============================================================================

 // 4) INTERRUPT GENERATION

 //============================================================================

 // Port 2 interrupt

 //------------------

 // Delay input // The p2in_dly stores former value of p2in, it will be used for edge detection

 reg    [:] p2in_dly;

 always @ (posedge mclk or posedge puc_rst)

   if (puc_rst)  p2in_dly <=  'h00;

   else          p2in_dly <=  p2in & P2_EN_MSK;    

 // Edge detection // Now we can detect rising and falling edge easily by combining p2in and p2in_dly

 wire   [:] p2in_re   =   p2in & ~p2in_dly;

 wire   [:] p2in_fe   =  ~p2in &  p2in_dly;

 // Set interrupt flag // p2ies register decide which edge is interrup signal; p2ifg_set is sent to p2ifg for interrupt flag

 assign       p2ifg_set = {p2ies[] ? p2in_fe[] : p2in_re[],

                           p2ies[] ? p2in_fe[] : p2in_re[],

                           p2ies[] ? p2in_fe[] : p2in_re[],

                           p2ies[] ? p2in_fe[] : p2in_re[],

                           p2ies[] ? p2in_fe[] : p2in_re[],

                           p2ies[] ? p2in_fe[] : p2in_re[],

                           p2ies[1] ? p2in_fe[] : p2in_re[],

                           p2ies[] ? p2in_fe[] : p2in_re[]} & P2_EN_MSK;

 // Generate CPU interrupt // Interrupt is generated when interrupt is enabled and p2ifg (interrupt flag) is available

 assign       irq_port2 = |(p2ie & p2ifg) & P2_EN[];

 // Delay input

 reg    [:] p2in_dly;

 always @ (posedge mclk or posedge puc_rst)

   if (puc_rst)  p2in_dly <=  'h00;

   else          p2in_dly <=  p2in;    

 // Edge detection

 wire   [:] p2in_re   =   p2in & ~p2in_dly;

 // Set interrupt flag

 assign       p2ifg_set = { p2in_re[],

                            p2in_re[],

                            p2in_re[],

                            p2in_re[],

                            p2in_re[],

                            p2in_re[],

                            p2in_re[],

                            p2in_re[]　　};

 // Generate CPU interrupt

 assign      irq_port2 = | p2ifg;

 // P2IFG Register

 //----------------

 reg  [:] p2ifg;

 wire       p2ifg_wr  = P2IFG[] ? reg_hi_wr[P2IFG] : reg_lo_wr[P2IFG];

 wire [:] p2ifg_nxt = P2IFG[] ? per_din[:]    : per_din[:];

 wire [:] p2ifg_set;

 always @ (posedge mclk or posedge puc_rst)

   if (puc_rst)        p2ifg <=  'h00;

   else if (p2ifg_wr)  p2ifg <=  (p2ifg_nxt | p2ifg_set) & P2_EN_MSK;

   else                p2ifg <=  (p2ifg     | p2ifg_set) & P2_EN_MSK;

   // P2IFG Register

   //----------------

   reg  [:] p2ifg;

   wire       p2ifg_wr  =  reg_hi_wr[]; // If decoded address is P2IFG, then write it into data

   wire [:] p2ifg_nxt =  per_din[:]; // receive high byte data from openMSP

   wire [:] p2ifg_set;

   always @ (posedge mclk or posedge puc_rst)

    if (puc_rst)        p2ifg <=  'h00;

    else if (p2ifg_wr)  p2ifg <=  p2ifg_nxt | p2ifg_set; // write into

    else                p2ifg <=  p2ifg     | p2ifg_set; // read out