//如果是8位的话，只选择低8位传输

 //因为同步码也是可以自己设置，所以把同步码设置成parameter最好

 module embeded_2_separate_sync(

         input clk,

         input [:] din,

         output[:] dout,

         output h_black_out,//包括同步码在内的Black

         output v_black_out,//包括同步码在内的Black

         output h_no_sync_black_out,//不包括同步码在内的Black

         output h_sync_black_out,//只在4个同步码周期为高电平

         output de_o,

         output reg [:] line_cnt//计算行数

     );

     parameter VAL_SAV = 'h80;

     parameter VAL_EAV = 'h9d;

     parameter IVAL_SAV = 'hab;

     parameter IVAL_EAV = 'hb6;

     parameter DATA_WIDTH = ;

     reg [DATA_WIDTH-:] v_data [:] ;

     always @( posedge clk )

     begin

         v_data[] <= din;

     end

     genvar  i  ;

     generate 

         for( i = ;i <= ;i = i+ )

         begin :data_dly

          always@( posedge clk )begin

                     v_data[i+] <= v_data[i];

             end

             assign dout = v_data[];  

         end

     endgenerate

     wire [:] time_ref_code;

     reg    [:] time_ref_code_r = ;

     assign time_ref_code[] = (v_data[][:] == 'hff  ) ? 1'b1 : 'b0;

     assign time_ref_code[] = (v_data[][:] == 'h00  ) ? 1'b1 : 'b0;

     assign time_ref_code[] = (v_data[][:] == 'h00  ) ? 1'b1 : 'b0;

     assign time_ref_code[] = (v_data[][:] ==VAL_SAV ) ?'b1 : 1'b0;

     assign time_ref_code[] = (v_data[][:] ==VAL_EAV ) ?'b1 : 1'b0;

     assign time_ref_code[] = (v_data[][:] ==IVAL_SAV) ?'b1 : 1'b0;

     assign time_ref_code[] = (v_data[][:] ==IVAL_EAV) ?'b1 : 1'b0;

     always @( posedge clk )

     begin

             time_ref_code_r <= time_ref_code;

     end

 //    reg h_sync;

 //    reg v_sync;

     reg    h_sync_r = ;

     reg    v_sync_r = ;

     always @( posedge clk  )

     begin

             case(time_ref_code_r )

                 'h71 :begin  h_sync_r = 1'b0; v_sync_r = 'b0; end

                 'h72 :begin  h_sync_r = 1'b1; v_sync_r = 'b0; end

                 'h74 :begin  h_sync_r = 1'b0; v_sync_r = 'b1; end

                 'h78 :begin  h_sync_r = 1'b1; v_sync_r = 'b1; end

                 default : begin h_sync_r = h_sync_r; v_sync_r = v_sync_r; end

             endcase

     end

     reg [:] h_sync_dly = ;

     reg [:] v_sync_dly = ;

     always @( posedge clk )

     begin

             h_sync_dly[:] <= {h_sync_dly[:],h_sync_r};

             v_sync_dly[:] <= {v_sync_dly[:],v_sync_r};

     end

     reg [:] h_sync_r2 = 'b00;

     reg [:] v_sync_r2 = 'b00;

     always @( posedge clk )

     begin

         v_sync_r2[:]  <= {v_sync_r2[],v_sync_r};

         h_sync_r2[:]  <= {h_sync_r2[],h_sync_r};

     end

     wire pos_h = (h_sync_r2 == 'b01);

     wire pos_v = (v_sync_r2 == 'b01);

     always @( posedge clk )

     begin

         if( pos_v )

             line_cnt <= ;

         else if( pos_h )

             line_cnt <= line_cnt + 'b1;

         else

             line_cnt <= line_cnt;

     end

     wire h_black ;

     wire h_no_sync_black;

     wire h_sync_black;

     reg h_black_r = ;

     reg v_black_r = ;

     reg h_no_sync_black_r = ;

     reg h_sync_black_r = ;

     reg h_sync_orign_r = ;

     reg de_r = ;

     assign h_black = h_sync_r | h_sync_dly[] ;

     assign h_no_sync_black =  h_sync_r & h_sync_dly[] ;

     assign h_sync_black = h_black^h_no_sync_black ;

     always @( posedge clk )

     begin

             h_black_r <= h_black;

             de_r <= v_sync_r ?  :~h_black;

             v_black_r <= v_sync_r;

             h_no_sync_black_r <= h_no_sync_black;

             h_sync_black_r <= h_sync_black;

             h_sync_orign_r <= h_sync_r;

     end

     assign h_black_out = h_black_r;

     assign v_black_out = v_black_r;

     assign h_no_sync_black_out = h_no_sync_black_r;

     assign h_sync_black_out = h_sync_black_r;

     assign de_o = de_r;

     endmodule