HDLBits答案——Circuits
2024-09-08 05:17:36
1 Combinational Logic
1.1 Basic Gates
1.1.1 Exams/m2014 q4h
module top_module (
input in,
output out);
assign out = in;
endmodule
1.1.2 Exams/m2014 q4i
module top_module (
output out);
assign out = 1'b0;
endmodule
1.1.3 Exams/m2014 q4e
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1|in2);
endmodule
1.1.4 Exams/m2014 q4f
module top_module (
input in1,
input in2,
output out);
assign out = in1&(~in2);
endmodule
1.1.5 Exams/m2014 q4g
module top_module (
input in1,
input in2,
input in3,
output out);
wire out1;
assign out1 = in1^in2;
assign out = ~(out1^in3);
endmodule
1.1.6 Gates
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a&b;
assign out_or = a|b;
assign out_xor = (a^b);
assign out_nand = ~(a&b);
assign out_nor = ~(a|b);
assign out_xnor = ~(a^b);
assign out_anotb = a&~b;
endmodule
1.1.7 7420
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a&p1b&p1c&p1d);
assign p2y = ~(p2a&p2b&p2c&p2d);
endmodule
1.1.8 Truthtable1
module top_module(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = (x3&x1)|(~x3&x2);
endmodule
1.1.9 Mt2015 eq2
module top_module ( input [1:0] A, input [1:0] B, output z );
always @(*)begin
if(A==B)
z = 1;
else
z = 0;
end
endmodule
1.1.10 Mt2015 q4a
module top_module (input x, input y, output z);
assign z = (x ^ y) & x;
endmodule
1.1.11 Mt2015 q4b
module top_module ( input x, input y, output z );
assign z = ~(x^y);
endmodule
1.1.12 Mt2015 q4
module top_module (input x, input y, output z);
wire [3:0] z_pr;
IA U1(x,y,z_pr[0]);
IB L1(x,y,z_pr[1]);
IA U2(x,y,z_pr[2]);
IB L2(x,y,z_pr[3]);
assign z = (z_pr[0]|z_pr[1])^(z_pr[2]&z_pr[3]);
endmodule
module IA(input a,input b, output c);
assign c = (a ^ b) & a;
endmodule
module IB(input a,input b, output c);
assign c = ~(a^b);
endmodule
1.1.13 Ringer
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = ring & (~vibrate_mode);
assign motor = ring & vibrate_mode;
endmodule
1.1.14 Thermostat
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode&too_cold;
assign aircon = too_hot&~mode;
assign fan = (heater | aircon) | fan_on;
endmodule
1.1.15 Popcount3
module top_module(
input [2:0] in,
output [1:0] out );
integer i;
always @(*) begin
out = 0;
for(i = 0; i < 3; i ++) begin
if(in[i])
out++;
end
end
endmodule
1.1.15 Popcount3
module top_module(
input [2:0] in,
output [1:0] out );
integer i;
always @(*) begin
out = 0;
for(i = 0; i < 3; i ++) begin
if(in[i])
out++;
end
end
endmodule
1.1.16 Gatesv
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
integer i;
always @(*)begin
for(i = 0;i<3;i++)
begin
out_both[i] = in[i]&in[i+1];
out_any[i+1] = in[i]|in[i+1];
out_different[i] = in[i]^in[i+1];
end
out_different[3] = in[3]^in[0];
end
endmodule
1.1.17 Gatesv100
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
integer i;
always @(*)begin
for(i = 0;i<99;i++)
begin
out_both[i] = in[i]&in[i+1];
out_any[i+1] = in[i]|in[i+1];
out_different[i] = in[i]^in[i+1];
end
out_different[99] = in[99]^in[0];
end
endmodule
1.2 Multiplexers
1.2.1 Mux2to1
module top_module(
input a, b, sel,
output out );
always @(*)begin
case(sel)
1'b0:out=a;
1'b1:out=b;
endcase
end
endmodule
1.2.2 Mux2to1v
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
always @(*)begin
case(sel)
1'b0:out=a;
1'b1:out=b;
endcase
end
endmodule
1.2.3 Mux9to1v
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always @(*) begin
case(sel)
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
4 : out = e;
5 : out = f;
6 : out = g;
7 : out = h;
8 : out = i;
default : out = 16'hffff;
endcase
end
endmodule
1.2.4 Mux256to1
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out = in[sel];
endmodule
1.2.5 Mux256to1v
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
assign out = {in[4*sel+3],in[4*sel+2],in[4*sel+1],in[4*sel]};
endmodule
1.3 Arithmetic Circuits
1.3.1 Hadd
module top_module(
input a, b,
output cout, sum );
assign sum = a^b;
assign cout = a&b;
endmodule
1.3.2 Fadd
module top_module(
input a, b, cin,
output cout, sum );
assign {cout,sum} = a+b+cin;
endmodule
1.3.3 Adder3
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
add1 U1(a[0],b[0],cin,sum[0],cout[0]);
genvar i;
generate
for(i=1;i<3;i++)begin: add
add1 Ui(a[i],b[i],cout[i-1],sum[i],cout[i]);
end
endgenerate
endmodule
module add1 ( input a, input b, input cin, output sum, output cout );
// Full adder module here
assign sum = a^b^cin;
assign cout = (a&b)|(a&cin)|(b&cin);
endmodule
1.3.4 Exams/m2014 q4j
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum);
wire [3:0] cout;
add1 U1(x[0],y[0], ,sum[0],cout[0]);
genvar i;
generate
for(i=1;i<3;i++)
begin:add
add1 Ui(x[i],y[i],cout[i-1],sum[i],cout[i]);
end
endgenerate
add1 U2(x[3],y[3],cout[2] ,sum[3] ,sum[4]);
endmodule
module add1 ( input a, input b, input cin, output sum, output cout );
// Full adder module here
assign sum = a^b^cin;
assign cout = (a&b)|(a&cin)|(b&cin);
endmodule
1.3.5 Exams/ece241 2014 q1c
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
// assign s = ...
// assign overflow = ...
assign s = a + b;
assign overflow = (a[7] == b[7] && a[7] != s[7]) ? 1 : 0;
endmodule
1.3.6 Adder100
module top_module(
input [99:0] a, b,
input cin,
output cout,
output [99:0] sum );
wire [99:0] cout_pr;
add1 U1(a[0],b[0],cin ,sum[0],cout_pr[0]);
genvar i;
generate
for(i=1;i<99;i++)
begin:add
add1 Ui(a[i],b[i],cout_pr[i-1],sum[i],cout_pr[i]);
end
endgenerate
add1 U2(a[99],b[99],cout_pr[98] ,sum[99] ,cout);
endmodule
module add1 ( input a, input b, input cin, output sum, output cout );
// Full adder module here
assign sum = a^b^cin;
assign cout = (a&b)|(a&cin)|(b&cin);
endmodule
1.3.7 Bcdadd4
module top_module(
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire [15:0] cout_pr;
bcd_fadd fadd(a[3:0], b[3:0], cin, cout_pr[0], sum[3:0]);
assign cout = cout_pr[12];
generate
genvar i;
for(i = 4; i < 16; i = i + 4) begin:adder
bcd_fadd fadd(a[i + 3:i], b[i + 3:i], cout_pr[i-4], cout_pr[i], sum[i + 3:i]);
end
endgenerate
endmodule
1.4 Karnaugh Map to Circuit
1.4.1 Kmap1
module top_module(
input a,
input b,
input c,
output out );
assign out = ~(~a & ~b & ~c);
endmodule
1.4.2 Kmap2
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = (~a&~b&~c)|(~a&~c&~d)|(~a&c&~d)|(b&c&d)|(a&c&d)|(a&~b&~c);
endmodule
1.4.3 Kmap3
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a|(~b&c);
endmodule
1.4.4 Kmap4
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a^b^c^d;
endmodule
1.4.5 Exams/ece241 2013 q2
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (~a & ~b & c) | (b & c & d) | (a & c & d);
assign out_pos = out_sop;
endmodule
1.4.6 Exams/m2014 q3
module top_module (
input [4:1] x,
output f );
assign f = ~((~x[2] & ~x[3] & x[4]) | (~x[1] & x[2] & ~x[3] & x[4]) | (x[1] & x[2] & x[3] & ~x[4]) | (~x[1] & x[2] & ~x[3] & ~x[4]));
endmodule
1.4.7 Exams/2012 q1g
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1] & x[3]) | (~x[2] & ~x[3] & ~x[4]) | (x[1] & ~x[2] & x[3] & ~x[4]) | (x[2] & x[3] & x[4]);
endmodule
1.4.8 Exams/ece241 2014 q3
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c | d;
assign mux_in[1] = 0;
assign mux_in[2] = ~d;
assign mux_in[3] = c & d;
endmodule
2 Sequential logic
2.1 Latches and Flip-Flops
2.1.1 Dff
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q );//
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk)begin
q <= d;
end
endmodule
2.1.2 Dff8
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk)begin
q <= d;
end
endmodule
2.1.3 Dff8r
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk)begin
if(reset) begin
q = 0;
end
else begin
q <= d;
end
end
endmodule
2.1.3 Dff8p
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk)begin
if(reset) begin
q = 8'h0x34;
end
else begin
q <= d;
end
end
endmodule
2.1.4 Dff8ar
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset)begin
if(areset) begin
q = 0;
end
else begin
q <= d;
end
end
endmodule
2.1.5 Dff16e
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk)begin
if(resetn) begin
case(byteena)
2'b01:q[7:0] = d[7:0];
2'b10:q[15:8] = d[15:8];
2'b11:q = d;
default:q=q;
endcase
end
else begin
q = 0;
end
end
endmodule
2.1.6 Exams/m2014 q4a
module top_module (
input d,
input ena,
output q);
always @(*) begin
if(ena) begin
q = d;
end
end
endmodule
2.1.7 Exams/m2014 q4b
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q);
always @(posedge clk or posedge ar)begin
if(ar)
q <= 0;
else
q <= d;
end
endmodule
2.1.8 Exams/m2014 q4c
module top_module (
input clk,
input d,
input r, // synchronous reset
output q);
always @(posedge clk)begin
if(r)
q <= 0;
else
q <= d;
end
endmodule
2.1.9 Exams/m2014 q4d
module top_module (
input clk,
input in,
output out);
always @(posedge clk)begin
out = in^out;
end
endmodule
2.1.10 Mt2015 muxdff
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
wire temp;
assign temp = L ? r_in : q_in;
always @ (posedge clk )
begin
Q <= temp;
end
endmodule
2.1.11 Exams/2014 q4a
module top_module (
input clk,
input w, R, E, L,
output Q
);
wire temp0,temp1;
assign temp0 = (E)? w:Q;
assign temp1 = (L)? R:temp0;
always @(posedge clk) begin
Q <= temp1;
end
endmodule
2.1.12 Exams/ece241 2014 q4
module top_module (
input clk,
input x,
output z
);
reg [2:0] Q;
always @(posedge clk) begin
Q[0] <= Q[0]^x;
Q[1] <= ~Q[1]&x;
Q[2] <= ~Q[2]|x;
end
assign z = ~(|Q);
endmodule
2.1.13 Exams/ece241 2014 q7
module top_module (
input clk,
input j,
input k,
output Q);
always @(posedge clk)
begin
case ({j, k})
2'b00: Q <= Q;
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= ~Q;
endcase
end
endmodule
2.1.14 Edgedetect
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] temp;
always @(posedge clk) begin
temp <= in;
pedge <= in&~temp;
end
endmodule
2.1.15 Edgedetect2
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] temp;
always @(posedge clk) begin
temp <= in;
anyedge <= in^temp;
end
endmodule
2.1.16 Edgecapture
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] temp;
always @(posedge clk) begin
if(reset)
begin
out <= 0;
temp <= in;
end
else
begin
temp <= in;
out <= ~in&temp|out;
end
end
endmodule
2.1.18 Dualedge
module top_module (
input clk,
input d,
output q
);
reg [1:0] state;
always @(posedge clk) begin
state[0] <= d;
end
always @(negedge clk) begin
state[1] <= d;
end
assign q = (clk)? state[0]:state[1];
endmodule
2.2 Counters
2.2.1 Count15
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always @(posedge clk) begin
if(reset) q = 0;
else q++;
end
endmodule
2.2.2 Count10
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always @(posedge clk) begin
if(reset||q==9) q = 0;
else q++;
end
endmodule
2.2.3 Count1to10
module top_module (
input clk,
input reset,
output [3:0] q);
always @(posedge clk) begin
if(reset||q==10) q = 1;
else q++;
end
endmodule
2.2.4 Countslow
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always @(posedge clk) begin
if(reset)
q = 0;
else if(q==9&&slowena)
q = 0;
else if(slowena)
q++;
end
endmodule
2.2.5 Exams/ece241 2014 q7a
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable;
assign c_load = reset|(Q==12&enable);
assign c_d = (c_load)? 1:0;
//count4 the_counter (clk, c_enable, c_load, c_d /*, ... */ );
count4 the_counter (clk, c_enable, c_load, c_d, Q);
endmodule
2.2.6 Exams/ece241 2014 q7b
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
wire [3:0] q0,q1,q2;
assign c_enable = {q1 == 4'd9&&q0 == 4'd9, q0 == 4'd9, 1'd1};
assign OneHertz = (q2 == 4'd9&&q1 == 4'd9&&q0 == 4'd9);
bcdcount counter0 (clk, reset, c_enable[0], q0);
bcdcount counter1 (clk, reset, c_enable[1], q1);
bcdcount counter2 (clk, reset, c_enable[2], q2);
endmodule
2.2.7 Countbcd
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
reg [3:0] ones;
reg [3:0] tens;
reg [3:0] hundreds;
reg [3:0] thousands;
always@(posedge clk)begin
if(reset)begin
ones <= 4'd0;
end
else if(ones == 4'd9)begin
ones <= 4'd0;
end
else begin
ones <= ones + 1'b1;
end
end
always@(posedge clk)begin
if(reset)begin
tens <= 4'd0;
end
else if(tens == 4'd9&&ones == 4'd9)begin
tens <= 4'd0;
end
else if(ones == 4'd9)begin
tens <= tens + 1'b1;
end
end
always@(posedge clk)begin
if(reset)begin
hundreds <= 4'd0;
end
else if(hundreds == 4'd9&&tens == 4'd9&&ones == 4'd9)begin
hundreds <= 4'd0;
end
else if(tens == 4'd9&&ones == 4'd9)begin
hundreds <= hundreds + 1'b1;
end
end
always@(posedge clk)begin
if(reset)begin
thousands <= 4'd0;
end
else if(thousands == 4'd9&&hundreds == 4'd9&&tens == 4'd9&&ones == 4'd9)begin
thousands <= 4'd0;
end
else if(hundreds == 4'd9&&tens == 4'd9&&ones == 4'd9)begin
thousands <= thousands + 1'b1;
end
end
assign q = {thousands, hundreds, tens, ones};
assign ena[1] = (ones == 4'd9)? 1:0;
assign ena[2] = (ones == 4'd9&&tens == 9)? 1:0;
assign ena[3] = (ones == 4'd9&&tens == 9&&hundreds == 4'd9) ? 1:0;
endmodule
2.2.8 Count clock
module top_module(
input clk,
input reset,
input ena,
output reg pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
reg [3:0] ss_l,ss_h,mm_l,mm_h,hh_l,hh_h;
always @(posedge clk) begin
if(reset)
ss_l <= 0;
else if(~ena);
else if(ss_l<4'd9)
ss_l <= ss_l+1;
else if(ss_l == 4'd9)
ss_l <= 0;
end
always @(posedge clk) begin
if(reset)
ss_h <= 0;
else if(~ena);
else if(ss_l==4'd9&&ss_h<4'd5)
ss_h <= ss_h +1;
else if(ss_h == 4'd5&&ss_l == 4'd9)
ss_h <= 0;
end
always @(posedge clk) begin
if(reset)
mm_l <= 0;
else if(ss_h==4'd5&&ss_l == 4'd9&&mm_l<4'd9)
mm_l <= mm_l +1;
else if(ss_h==4'd5&&ss_l == 4'd9&&mm_l == 4'd9)
mm_l <= 0;
end
always @(posedge clk) begin
if(reset)
mm_h <= 0;
else if(ss_l == 4'd9&&ss_h == 4'd5&&mm_l==4'd9&&mm_h<4'd5)
mm_h <= mm_h +1;
else if(ss_l == 4'd9&&ss_h == 4'd5&&mm_h == 4'd5&&mm_l == 4'd9)
mm_h <= 0;
end
always @(posedge clk) begin
if(reset)
hh_l <= 2;
else if((ss_l==4'd9&&ss_h==4'd5&&mm_h == 4'd5&&mm_l == 4'd9&&hh_h==4'd0&&hh_l<4'd9)||(ss_l==4'd9&&ss_h==4'd5&&mm_h == 4'd5&&mm_l == 4'd9&&hh_h==4'd1&&hh_l<4'd2))
hh_l <= hh_l +1;
else if(ss_l==4'd9&&ss_h==4'd5&&mm_h == 4'd5&&mm_l == 4'd9&&hh_h==4'd0&&hh_l==4'd9)
hh_l <= 0;
else if(ss_l==4'd9&&ss_h==4'd5&&mm_h == 4'd5&&mm_l == 4'd9&&hh_h==4'd1&&hh_l==4'd2)
hh_l <= 1;
end
always @(posedge clk) begin
if(reset)begin
hh_h <= 1;
pm <= 1'b0;
end
else if(ss_l==4'd9&&ss_h==4'd5&&mm_h == 4'd5&&mm_l == 4'd9&&hh_h==4'd0&&hh_l==4'd9)
hh_h <= hh_h + 1;
else if(ss_l==4'd9&&ss_h==4'd5&&mm_h == 4'd5&&mm_l == 4'd9&&hh_h==4'd1&&hh_l==4'd2)begin
hh_h <= 0;
end
if(ss_l==4'd9&&ss_h==4'd5&&mm_h == 4'd5&&mm_l == 4'd9&&hh_h==4'd1&&hh_l==4'd1)begin
pm <= ~pm;
end
end
assign ss = {ss_h,ss_l};
assign mm = {mm_h,mm_l};
assign hh = {hh_h,hh_l};
endmodule
2.3 Shift Registers
2.3.1 Shift4
module top_module(
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always @(posedge clk or posedge areset) begin
if(areset)
q = 4'd0;
else begin
if(load)
q = data;
else if(ena)
q = q>>1;
end
end
endmodule
2.3.2 Rotate100
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always@(posedge clk)begin
if(load)begin
q <= data;
end
else begin
case(ena)
2'b00, 2'b11:begin
q <= q;
end
2'b01:begin
q <= {q[0], q[99:1]};
end
2'b10:begin
q <= {q[98:0], q[99]};
end
endcase
end
end
endmodule
2.3.3 Shift18
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if(load)
q = data;
else begin
if(ena) begin
case(amount)
2'b00: q = q<<1;
2'b01: q = q<<8;
2'b10: q = {q[63],q[63:1]};
2'b11: q = {{8{q[63]}},q[63:8]};
endcase
end
else
q = q;
end
end
endmodule
2.3.4 Lfsr5
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk) begin
if(reset)
q = 5'h1;
else begin
q[4] <= q[0];
q[3] <= q[4];
q[2] <= q[3] ^ q[0];
q[1] <= q[2];
q[0] <= q[1];
end
end
endmodule
2.3.5 Mt2015 lfsr
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
wire temp;
assign temp = LEDR[1]^LEDR[2];
always @(posedge KEY[0]) begin
LEDR[0] <= (KEY[1])? SW[0]:LEDR[2];
LEDR[1] <= (KEY[1])? SW[1]:LEDR[0];
LEDR[2] <= (KEY[1])? SW[2]:temp;
end
endmodule
2.3.6 Lfsr32
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] q_next;
always@(*)begin
q_next = {q[0], q[31:1]};
q_next[21] = q[0] ^ q[22];
q_next[1] = q[0] ^ q[2];
q_next[0] = q[0] ^ q[1];
end
always@(posedge clk)begin
if(reset)begin
q <= 32'd1;
end
else begin
q <= q_next;
end
end
endmodule
2.3.7 Exams/m2014 q4k
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg [3:0] out_temp;
always@(posedge clk)begin
if(resetn == 1'b0)begin
out_temp <= 4'd0;
end
else begin
out_temp <= {out_temp[2:0], in};
end
end
assign out = out_temp[3];
endmodule
2.3.8 Exams/2014 q4b
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
MUXDFF U1(.clk(KEY[0]),
.w(KEY[3] ),
.R(SW[3] ),
.E(KEY[1] ),
.L(KEY[2] ),
.Q(LEDR[3])
);
MUXDFF U2(.clk(KEY[0]),
.w(LEDR[3]),
.R(SW[2] ),
.E(KEY[1] ),
.L(KEY[2] ),
.Q(LEDR[2])
);
MUXDFF U3(.clk(KEY[0]),
.w(LEDR[2]),
.R(SW[1] ),
.E(KEY[1] ),
.L(KEY[2] ),
.Q(LEDR[1])
);
MUXDFF U4(.clk(KEY[0]),
.w(LEDR[1]),
.R(SW[0] ),
.E(KEY[1] ),
.L(KEY[2] ),
.Q(LEDR[0])
);
endmodule
module MUXDFF (
input clk,
input w, R, E, L,
output Q
);
wire temp0,temp1;
assign temp0 = (E)? w:Q;
assign temp1 = (L)? R:temp0;
always @(posedge clk) begin
Q <= temp1;
end
endmodule
2.3.9 Exams/ece241 2013 q12
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output Z );
reg [7:0] Q;
always @(posedge clk) begin
if(enable)
Q <= {Q[6:0],S};
else
Q <= Q;
end
assign Z = Q[{A, B, C}];
endmodule
2.4 More Circuits
2.4.1 Rule90
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q );
always@(posedge clk)begin
if(load)begin
q <= data;
end
else begin
q <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0};
end
end
endmodule
2.4.2 Rule110
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @(posedge clk) begin
if (load) begin
q <= data;
end
else begin
q <= (((q[511:0] ^ {q[510:0], 1'b0}) & q[511:1]) | ((q[511:0] | {q[510:0], 1'b0}) & (~q[511:1])));
end
end
endmodule
2.4.3 Conwaylife
module top_module(
input clk,
input load,
input [255:0] data,
output [255:0] q );
integer i;
reg [3:0] sum;
always @(posedge clk) begin
if(load)
q = data;
else begin
for(i=0;i<256;i++) begin
if(i==0)
sum = q[255] + q[240] + q[241] + q[15] + q[1] + q[31] + q[16] + q[17];
else if(i == 15)
sum = q[254] + q[255] + q[240] + q[14] + q[0] + q[30] + q[31] + q[16];
else if(i == 240)
sum = q[239] + q[224] + q[225] + q[255] + q[241] + q[15] + q[0] + q[1];
else if(i == 255)
sum = q[238] + q[239] + q[224] + q[254] + q[240] + q[14] + q[15] + q[0];
else if(i>0&&i<15)
sum = q[i-1] + q[i+1] + q[i+15] + q[i+16] + q[i+17] + q[i+239] + q[i+240] + q[i+241];
else if(i>240&&i<255)
sum = q[i-1] + q[i+1] + q[i-15] + q[i-16] + q[i-17] + q[i-239] + q[i-240] + q[i-241];
else if(i%16 == 0)
sum = q[i-1] + q[i-16] + q[i-15] + q[i+15] + q[i+1] + q[i+31] + q[i+16] + q[i+17];
else if(i%16 == 15)
sum = q[i-17] + q[i-16] + q[i-31] + q[i-1] + q[i-15] + q[i+15] + q[i+16] + q[i+1];
else
sum = q[i-17] + q[i-16] + q[i-15] + q[i-1] + q[i+1] + q[i+15] + q[i+16] + q[i+17];
if(sum<=1||sum>=4) q[i] <= 0;
else if(sum == 4'd3) q[i] <= 1;
else q[i] <= q[i];
end
end
end
endmodule
2.5 Finite State Machines
2.5.1 Fsm1
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case(state)
A:next_state <= in ? A:B;
B:next_state <= in ? B:A;
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if(areset)
state <= B;
else
state <= next_state;
end
assign out = (state==B)? 1:0;
// Output logic
// assign out = (state == ...);
endmodule
2.5.2 Fsm1s
// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A=0,B=1;
reg present_state, next_state;
always @(*) begin
case(present_state)
A:begin next_state = ~in;out = A;end
B:begin next_state = in;out = B;end
endcase
end
always @(posedge clk) begin
if(reset)
present_state = B;
else begin
present_state = next_state;
end
end
endmodule
2.5.3 Fsm2
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
0:next_state <= j;
1:next_state <= ~k;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)
state <= 0;
else
state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = state;
endmodule
2.5.4 Fsm2s
module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
0:next_state <= j;
1:next_state <= ~k;
endcase
end
always @(posedge clk) begin
// State flip-flops with asynchronous reset
if(reset)
state <= 0;
else
state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = state;
endmodule
2.5.5 Fsm3comb
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case(state)
A:next_state = in;
B:next_state = (in)? B:C;
C:next_state = (in)? D:A;
D:next_state = (in)? B:C;
endcase
end
// Output logic: out = f(state) for a Moore state machine
assign out = (state==D);
endmodule
2.5.6 Fsm3onehot
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[A] & ~in | state[C] & ~in;
assign next_state[B] = state[A] & in | state[B] & in | state[D] & in;
assign next_state[C] = state[B] & ~in | state[D] & ~in;
assign next_state[D] = state[C] & in;
// Output logic:
assign out = state[D];
endmodule
2.5.7 Fsm3
module top_module(
input clk,
input in,
input areset,
output out); //
reg [1:0] state,next_state;
parameter A=0,B=1,C=2,D=3;
// State transition logic
always @(*) begin
case(state)
A:next_state = in;
B:next_state = (in)? B:C;
C:next_state = (in)? D:A;
D:next_state = (in)? B:C;
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk or posedge areset) begin
if(areset)
state <= A;
else
state = next_state;
end
// Output logic
assign out = (state==D);
endmodule
2.5.8 Fsm3s
module top_module(
input clk,
input in,
input reset,
output out); //
reg [1:0] state,next_state;
parameter A=0,B=1,C=2,D=3;
// State transition logic
always @(*) begin
case(state)
A:next_state = in;
B:next_state = (in)? B:C;
C:next_state = (in)? D:A;
D:next_state = (in)? B:C;
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk) begin
if(reset)
state <= A;
else
state = next_state;
end
// Output logic
assign out = (state==D);
endmodule
2.5.9 Exams/ece241 2013 q4
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
reg [2:0] state,next_state;
always @(posedge clk) begin
if(reset)
state <= 0;
else
state <= next_state;
end
always @(*) begin
case(state)
3'b000:next_state = (s[1]) ? 3'b001:3'b000;
3'b001:next_state = (s[2]) ? 3'b011:(s[1]) ? 3'b001:3'b000;
3'b010:next_state = (s[2]) ? 3'b011:(s[1]) ? 3'b010:3'b000;
3'b011:next_state = (s[3]) ? 3'b101:(s[2]) ? 3'b011:3'b010;
3'b100:next_state = (s[3]) ? 3'b101:(s[2]) ? 3'b100:3'b010;
3'b101:next_state = (s[3]) ? 3'b101:3'b100;
default: next_state = 3'bxxx;
endcase
end
always @(*) begin
case(state)
3'b000: {fr3, fr2, fr1, dfr} = 4'b1111;
3'b001: {fr3, fr2, fr1, dfr} = 4'b0110;
3'b010: {fr3, fr2, fr1, dfr} = 4'b0111;
3'b011: {fr3, fr2, fr1, dfr} = 4'b0010;
3'b100: {fr3, fr2, fr1, dfr} = 4'b0011;
3'b101: {fr3, fr2, fr1, dfr} = 4'b0000;
default: {fr3, fr2, fr1, dfr} = 4'bxxxx;
endcase
end
endmodule
2.5.10 Lemmings1
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right); //
// parameter LEFT=0, RIGHT=1, ...
reg state, next_state;
parameter LEFT=0, RIGHT=1;
always @(*) begin
// State transition logic
case(state)
LEFT: begin
if(bump_left)
next_state <= RIGHT;
else
next_state <= state;
end
RIGHT: begin
if(bump_right)
next_state <= LEFT;
else
next_state <= state;
end
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)
state <= LEFT;
else
state <= next_state;
end
// Output logic
// assign walk_left = (state == ...);
// assign walk_right = (state == ...);
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
endmodule
2.5.11 Lemmings2
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah );
// parameter LEFT=0, RIGHT=1, ...
parameter LEFT = 2'd0, RIGHT = 2'd1, GROUND_LEFT = 2'd2, GROUND_RIGHT = 2'd3;
reg [1:0] current_state;
reg [1:0] next_state;
always@(posedge clk or posedge areset)begin
if(areset)begin
current_state <= LEFT;
end
else begin
current_state <= next_state;
end
end
always@(*)begin
case(current_state)
LEFT:begin
next_state = ground ? (bump_left ? RIGHT : LEFT) : GROUND_LEFT;
end
RIGHT:begin
next_state = ground ? (bump_right ? LEFT : RIGHT) : GROUND_RIGHT;
end
GROUND_LEFT:begin
next_state = ground ? LEFT : GROUND_LEFT;
end
GROUND_RIGHT:begin
next_state = ground ? RIGHT : GROUND_RIGHT;
end
default:begin
next_state = LEFT;
end
endcase
end
assign walk_left = (current_state == LEFT);
assign walk_right = (current_state == RIGHT);
assign aaah = (current_state == GROUND_LEFT || current_state == GROUND_RIGHT);
endmodule
2.5.12 Lemmings3
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter LEFT = 4'd0, RIGHT = 4'd1, GROUND_LEFT = 4'd2, GROUND_RIGHT = 4'd3;
parameter DIGGING_LEFT = 4'd4, DIGGING_RIGHT = 4'd5;
reg [3:0] state;
reg [3:0] next_state;
always@(posedge clk or posedge areset)begin
if(areset)begin
state <= LEFT;
end
else begin
state <= next_state;
end
end
always@(*)begin
case(state)
LEFT:begin
next_state = ground ? (dig ? DIGGING_LEFT : (bump_left ? RIGHT : LEFT)) : GROUND_LEFT;
end
RIGHT:begin
next_state = ground ? (dig ? DIGGING_RIGHT : (bump_right ? LEFT : RIGHT)) : GROUND_RIGHT;
end
GROUND_LEFT:begin
next_state = ground ? LEFT : GROUND_LEFT;
end
GROUND_RIGHT:begin
next_state = ground ? RIGHT : GROUND_RIGHT;
end
DIGGING_LEFT:begin
next_state = ground ? DIGGING_LEFT : GROUND_LEFT;
end
DIGGING_RIGHT:begin
next_state = ground ? DIGGING_RIGHT : GROUND_RIGHT;
end
default:begin
next_state = LEFT;
end
endcase
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
assign digging = (state == DIGGING_LEFT || state == DIGGING_RIGHT);
assign aaah = (state == GROUND_LEFT || state == GROUND_RIGHT);
endmodule
2.5.12 Lemmings3
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter LEFT = 4'd0, RIGHT = 4'd1, GROUND_LEFT = 4'd2, GROUND_RIGHT = 4'd3;
parameter DIGGING_LEFT = 4'd4, DIGGING_RIGHT = 4'd5;
reg [3:0] state;
reg [3:0] next_state;
always@(posedge clk or posedge areset)begin
if(areset)begin
state <= LEFT;
end
else begin
state <= next_state;
end
end
always@(*)begin
case(state)
LEFT:begin
next_state = ground ? (dig ? DIGGING_LEFT : (bump_left ? RIGHT : LEFT)) : GROUND_LEFT;
end
RIGHT:begin
next_state = ground ? (dig ? DIGGING_RIGHT : (bump_right ? LEFT : RIGHT)) : GROUND_RIGHT;
end
GROUND_LEFT:begin
next_state = ground ? LEFT : GROUND_LEFT;
end
GROUND_RIGHT:begin
next_state = ground ? RIGHT : GROUND_RIGHT;
end
DIGGING_LEFT:begin
next_state = ground ? DIGGING_LEFT : GROUND_LEFT;
end
DIGGING_RIGHT:begin
next_state = ground ? DIGGING_RIGHT : GROUND_RIGHT;
end
default:begin
next_state = LEFT;
end
endcase
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
assign digging = (state == DIGGING_LEFT || state == DIGGING_RIGHT);
assign aaah = (state == GROUND_LEFT || state == GROUND_RIGHT);
endmodule
2.5.13 Lemmings4
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
reg [2:0] state,next_state;
parameter LEFT = 3'd0,RIGHT = 3'd1,DIG_L = 3'd2,DIG_R = 3'd3,FALL_L = 3'd4,FALL_R = 3'd5,SPLAT = 3'd6,AAAH_END=3'd7;
reg [4:0] count;
always@(posedge clk or posedge areset) begin
if(areset)begin
count <= 5'd0;
end
else if(next_state == FALL_L || next_state == FALL_R)begin
count <= count + 1'b1;
end
else begin
count <= 5'd0;
end
end
always@(posedge clk or posedge areset) begin
if(areset) begin
state <= LEFT;
end
else begin
state <= next_state;
end
end
always@(*)begin
case(state)
LEFT:next_state <= ground ? (dig ? DIG_L:bump_left ? RIGHT:LEFT):FALL_L;
RIGHT:next_state <= ground ? (dig ? DIG_R:bump_right ? LEFT:RIGHT):FALL_R;
DIG_L:next_state <= ground ? DIG_L:FALL_L;
DIG_R:next_state <= ground ? DIG_R:FALL_R;
FALL_L:next_state <= ground ? LEFT:((count==20)? SPLAT:FALL_L);
FALL_R:next_state <= ground ? RIGHT:((count==20)? SPLAT:FALL_R);
SPLAT:next_state <= ground ? AAAH_END:SPLAT;
AAAH_END:next_state <= AAAH_END;
endcase
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
assign digging = (state == DIG_L || state == DIG_R);
assign aaah = (state == FALL_L || state == FALL_R || state == SPLAT);
endmodule
2.5.14 Fsm onehot
module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
assign next_state[0] = ~in & (state[0] | state[1] | state[2] | state[3] | state[4] | state[7] | state[8] | state[9]);
assign next_state[1] = in & (state[0] | state[8] | state[9]);
assign next_state[2] = in & state[1];
assign next_state[3] = in & state[2];
assign next_state[4] = in & state[3];
assign next_state[5] = in & state[4];
assign next_state[6] = in & state[5];
assign next_state[7] = in & (state[6] | state[7]);
assign next_state[8] = ~in & state[5];
assign next_state[9] = ~in & state[6];
assign out1 = state[8] | state[9];
assign out2 = state[9] | state[7];
endmodule
2.5.15 Fsm ps2
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done); //
reg [1:0] state,next_state;
// State transition logic (combinational)
always @(posedge clk) begin
if(reset)
state <= 2'd0;
else
state <= next_state;
end
// State flip-flops (sequential)
always @(*) begin
case(state)
2'd0:next_state <= in[3] ? 2'd1:2'd0;
2'd1:next_state <= 2'd2;
2'd2:next_state <= 2'd3;
2'd3:next_state <= in[3] ? 2'd1:2'd0;
endcase
end
// Output logic
assign done = (state==2'd3);
endmodule
2.5.16 Fsm ps2data
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //
// FSM from fsm_ps2
reg [1:0] state,next_state;
reg [23:0] out_reg;
// State transition logic (combinational)
always @(posedge clk) begin
if(reset)
state <= 2'd0;
else
state <= next_state;
end
// State flip-flops (sequential)
always @(*) begin
case(state)
2'd0:begin
next_state <= in[3] ? 2'd1:2'd0;
end
2'd1:begin
next_state <= 2'd2;
end
2'd2:begin
next_state <= 2'd3;
end
2'd3:begin
next_state <= in[3] ? 2'd1:2'd0;
end
endcase
end
always @(posedge clk) begin
case(state)
2'd0:begin
out_reg[23:16] <= in;
end
2'd1:begin
out_reg[15:8] <= in;
end
2'd2:begin
out_reg[7:0] <= in;
end
2'd3:begin
out_reg[23:16] <= in;
end
endcase
end
// Output logic
assign done = (state==2'd3);
assign out_bytes = done ? out_reg:23'd0;
endmodule
2.5.17 Fsm serial
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter IDLE = 4'd0, START = 4'd1, S1 = 4'd2, S2 = 4'd3, S3 = 4'd4, S4 = 4'd5;
parameter S5 = 4'd6, S6 = 4'd7, S7 = 4'd8, S8 = 4'd9, STOP = 4'd10, WAIT = 4'd11;
reg [3:0] state,next_state;
always @(posedge clk) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
case(state)
IDLE: next_state <= in? IDLE:START;
START: next_state <= S1;
S1: next_state <= S2;
S2: next_state <= S3;
S3: next_state <= S4;
S4: next_state <= S5;
S5: next_state <= S6;
S6: next_state <= S7;
S7: next_state <= S8;
S8: next_state <= in? STOP:WAIT;
STOP: next_state <= in? IDLE:START;
WAIT: next_state <= in? IDLE:WAIT;
endcase
end
assign done = (state == STOP);
endmodule
2.5.18 Fsm serialdata
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
// New: Datapath to latch input bits.
parameter IDLE = 4'd0, START = 4'd1, S1 = 4'd2, S2 = 4'd3, S3 = 4'd4, S4 = 4'd5;
parameter S5 = 4'd6, S6 = 4'd7, S7 = 4'd8, S8 = 4'd9, STOP = 4'd10, WAIT = 4'd11;
reg [3:0] state,next_state;
reg [7:0] out_reg;
always @(posedge clk) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
case(state)
IDLE: next_state <= in? IDLE:START;
START: next_state <= S1;
S1: next_state <= S2;
S2: next_state <= S3;
S3: next_state <= S4;
S4: next_state <= S5;
S5: next_state <= S6;
S6: next_state <= S7;
S7: next_state <= S8;
S8: next_state <= in? STOP:WAIT;
STOP: next_state <= in? IDLE:START;
WAIT: next_state <= in? IDLE:WAIT;
endcase
end
always @(posedge clk) begin
case(next_state)
S1: out_reg[0] <= in;
S2: out_reg[1] <= in;
S3: out_reg[2] <= in;
S4: out_reg[3] <= in;
S5: out_reg[4] <= in;
S6: out_reg[5] <= in;
S7: out_reg[6] <= in;
S8: out_reg[7] <= in;
default: out_reg <= out_reg;
endcase
end
assign done = (state == STOP);
assign out_byte = out_reg;
endmodule
2.5.19 Fsm serialdp
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Modify FSM and datapath from Fsm_serialdata
// New: Add parity checking.
parameter IDLE = 4'd0, START = 4'd1, S1 = 4'd2, S2 = 4'd3, S3 = 4'd4, S4 = 4'd5;
parameter S5 = 4'd6, S6 = 4'd7, S7 = 4'd8, S8 = 4'd9, check = 4'd10,STOP = 4'd11, WAIT = 4'd12;
reg [3:0] state,next_state;
reg [7:0] out_reg;
reg flag;
reg test;
always @(posedge clk) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
case(state)
IDLE: next_state <= in? IDLE:START;
START: next_state <= S1;
S1: next_state <= S2;
S2: next_state <= S3;
S3: next_state <= S4;
S4: next_state <= S5;
S5: next_state <= S6;
S6: next_state <= S7;
S7: next_state <= S8;
S8: next_state <= check;
check:next_state <= in? STOP:WAIT;
STOP: next_state <= in? IDLE:START;
WAIT: next_state <= in? IDLE:WAIT;
endcase
end
always @(posedge clk) begin
case(next_state)
S1: out_reg[0] <= in;
S2: out_reg[1] <= in;
S3: out_reg[2] <= in;
S4: out_reg[3] <= in;
S5: out_reg[4] <= in;
S6: out_reg[5] <= in;
S7: out_reg[6] <= in;
S8: out_reg[7] <= in;
check: flag <= in;
STOP:test <= in;
default: out_reg <= out_reg;
endcase
end
assign done = (state == STOP&&test==(^out_reg)^flag);
assign out_byte = out_reg;
endmodule
2.5.20 Fsm hdlc
module top_module(
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err);
reg [3:0] state,next_state;
parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,DISCARD=7,FLAG=8,ERROR=9;
always@(posedge clk)begin
if(reset)
state <= S0;
else
state <= next_state;
end
always@(*)begin
case(state)
S0:next_state <= in? S1:S0;
S1:next_state <= in? S2:S0;
S2:next_state <= in? S3:S0;
S3:next_state <= in? S4:S0;
S4:next_state <= in? S5:S0;
S5:next_state <= in? S6:DISCARD;
S6:next_state <= in? ERROR:FLAG;
DISCARD:next_state <= in? S1:S0;
FLAG: next_state <= in? S1:S0;
ERROR:next_state <= in? ERROR:S0;
default:next_state = S0;
endcase
end
assign disc = (state==DISCARD);
assign flag = (state==FLAG);
assign err = (state == ERROR);
endmodule
2.5.21 Exams/ece241 2013 q8
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z );
reg [1:0] state,next_state;
parameter S0=0,S1=1,S2=2;
always@(posedge clk or negedge aresetn)begin
if(~aresetn)
state <= S0;
else
state <= next_state;
end
always@(*)begin
case(state)
S0:next_state <= x ? S1:S0;
S1:next_state <= x? S1:S2;
S2:next_state <= x ? S1:S0;
endcase
end
assign z = (state==S2)&x;
endmodule
2.5.22 Exams/ece241 2014 q5a
module top_module (
input clk,
input areset,
input x,
output z
);
reg [1:0] state,next_state;
parameter S0=0,S1=1,S2=2,S3=3;
always@(posedge clk or posedge areset)begin
if(areset)
state <= S0;
else
state <= next_state;
end
always@(*)begin
case(state)
S0:next_state <= x ? S1:S0;
S1:next_state <= x ? S2:S1;
S2:next_state <= x ? S2:S1;
endcase
end
assign z = (state==S1);
endmodule
2.5.23 Exams/ece241 2014 q5b
module top_module (
input clk,
input areset,
input x,
output z
);
reg state,next_state;
parameter A=0,B=1;
always@(posedge clk or posedge areset)begin
if(areset)
state <= A;
else
state <= next_state;
end
always@(*)begin
case(state)
A:next_state <= x ? B:A;
B:next_state <= B;
endcase
end
assign z = (state==A)&x|(state==B)&~x;
endmodule
2.5.24 Exams/2014 q3fsm
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
reg state,next_state;
parameter A=1'd0,B=1'd1;
always@(posedge clk)begin
if(reset)
state <= A;
else
state <= next_state;
end
always@(*)begin
case(state)
A:next_state <= s ? B:A;
B:next_state <= B;
endcase
end
reg w_reg1;
reg w_reg2;
always@(posedge clk)begin
if(reset)begin
w_reg1 <= 1'b0;
w_reg2 <= 1'b0;
end
else if(next_state == B)begin
w_reg1 <= w;
w_reg2 <= w_reg1;
end
else begin
w_reg1 <= 1'b0;
w_reg2 <= 1'b0;
end
end
always@(posedge clk)begin
if(reset)begin
z <= 1'b0;
end
else if(state == B && counter == 2'd0)begin
if(~w & w_reg1 & w_reg2 | w & ~w_reg1 & w_reg2 | w & w_reg1 & ~w_reg2)begin
z <= 1'b1;
end
else begin
z <= 1'b0;
end
end
else begin
z <= 1'b0;
end
end
reg [1:0] counter;
always@(posedge clk)begin
if(reset)begin
counter <= 2'd0;
end
else if(counter == 2'd2)begin
counter <= 2'd0;
end
else if(next_state == B)begin
counter <= counter + 1'b1;
end
end
endmodule
2.5.25 Exams/2014 q3bfsm
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
reg [2:0] state,next_state;
always@(posedge clk)begin
if(reset)
state <= 3'b000;
else
state <= next_state;
end
always@(*)begin
case(state)
3'b000:begin
next_state <= x ? 3'b001:3'b000;
z <= 0;
end
3'b001:begin
next_state <= x ? 3'b100:3'b001;
z <= 0;
end
3'b010:begin
next_state <= x ? 3'b001:3'b010;
z <= 0;
end
3'b011:begin
next_state <= x ? 3'b010:3'b001;
z <= 1;
end
3'b100:begin
next_state <= x ? 3'b100:3'b011;
z <= 1;
end
default:next_state <= 3'b000;
endcase
end
endmodule
2.5.26 Exams/2014 q3c
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg [2:0] state,next_state;
always@(posedge clk)begin
state <= y;
end
always@(*)begin
case(y)
3'b000:begin
next_state <= x ? 3'b001:3'b000;
z <= 0;
end
3'b001:begin
next_state <= x ? 3'b100:3'b001;
z <= 0;
end
3'b010:begin
next_state <= x ? 3'b001:3'b010;
z <= 0;
end
3'b011:begin
next_state <= x ? 3'b010:3'b001;
z <= 1;
end
3'b100:begin
next_state <= x ? 3'b100:3'b011;
z <= 1;
end
default:next_state <= 3'b000;
endcase
end
always@(*)begin
Y0 <= next_state[0];
end
endmodule
2.5.27 Exams/m2014 q6b
module top_module (
input [3:1] y,
input w,
output Y2);
assign Y2 = (y == 3'b001 | y == 3'b101) & ~w |
(y == 3'b001 | y == 3'b010 | y == 3'b100 | y == 3'b101) & w;
endmodule
2.5.28 Exams/m2014 q6c
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4);
assign Y2 = y[1]&(~w);
assign Y4 = (y[2]|y[3]|y[5]|y[6])&w;
endmodule
2.5.29 Exams/m2014 q6
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z);
reg [2:0] state,next_state;
parameter A=0,B=1,C=2,D=3,E=4,F=5;
always@(posedge clk)begin
if(reset)
state <= A;
else
state <= next_state;
end
always@(*)begin
case(state)
A:begin
next_state <= w ? A:B;
z <= 0;
end
B:begin
next_state <= w ? D:C;
z <= 0;
end
C:begin
next_state <= w ? D:E;
z <= 0;
end
D:begin
next_state <= w ? A:F;
z <= 0;
end
E:begin
next_state <= w ? D:E;
z <= 1;
end
F:begin
next_state <= w ? D:C;
z <= 1;
end
endcase
end
endmodule
2.5.31 Exams/2012 q2fsm
module top_module (
input clk,
input reset, // Synchronous active-high reset
input w,
output z
);
reg [2:0] state,next_state;
parameter A=0,B=1,C=2,D=3,E=4,F=5;
always@(posedge clk)begin
if(reset)
state <= A;
else
state <= next_state;
end
always@(*)begin
case(state)
A:begin
next_state <= w ? B:A;
z <= 0;
end
B:begin
next_state <= w ? C:D;
z <= 0;
end
C:begin
next_state <= w ? E:D;
z <= 0;
end
D:begin
next_state <= w ? F:A;
z <= 0;
end
E:begin
next_state <= w ? E:D;
z <= 1;
end
F:begin
next_state <= w ? C:D;
z <= 1;
end
endcase
end
endmodule
2.5.32 Exams/2012 q2b
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = w & y[0];
assign Y3 = ~w & (y[1] | y[2] | y[4] | y[5]);
endmodule
2.5.33 Exams/2013 q2afsm
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
reg [1:0] state,next_state;
parameter A=2'b00,B=2'b01,C=2'b11,D=2'b10;
always@(posedge clk)begin
if(~resetn)
state <= A;
else
state <= next_state;
end
always@(*)begin
case(state)
A:begin
g <= 3'b000;
if(r[1])
next_state <= B;
else if(~r[1]&r[2])
next_state <= C;
else if(~r[1]&~r[2]&r[3])
next_state <= D;
else
next_state <= A;
end
B:begin
g <= 3'b001;
if(r[1])
next_state <= B;
else
next_state <= A;
end
C:begin
g <= 3'b010;
if(r[2])
next_state <= C;
else
next_state <= A;
end
D:begin
g <= 3'b100;
if(r[3])
next_state <= D;
else
next_state <= A;
end
endcase
end
endmodule
2.5.34 Exams/2013 q2bfsm
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
reg [3:0] state,next_state;
parameter A=4'b0000,B=4'b0001,S0=4'b0011,S1=4'b0010,S2=4'b0110,S3=4'b0111,
choose=4'b1111,forerver_zero=4'b1110,forerver_one=4'b1101;
always@(posedge clk)begin
if(~resetn)
state <= A;
else
state <= next_state;
end
always@(*)begin
case(state)
A:begin
next_state <= B;
f <= 0;
g <= 0;
end
B:begin
next_state <= S0;
f <= 1;
g <= 0;
end
S0:begin
next_state <= x ? S1:S0;
f <= 0;
g <= 0;
end
S1:begin
next_state <= x ? S1:S2;
f <= 0;
g <= 0;
end
S2:begin
next_state <= x ? S3:S0;
f <= 0;
g <= 0;
end
S3:begin
next_state <= y ? forerver_one:choose;
f <= 0;
g <= 1;
end
choose:begin
next_state <= y ? forerver_one:forerver_zero;
f <= 0;
g <= 1;
end
forerver_zero:begin
next_state <= forerver_zero;
f <= 0;
g <= 0;
end
forerver_one:begin
next_state <= forerver_one;
f <= 0;
g <= 1;
end
default:begin
next_state <= A;
f <= 0;
g <= 0;
end
endcase
end
endmodule
3 Building Larger Circuits
3.1 Exams/review2015 count1k
module top_module (
input clk,
input reset,
output [9:0] q);
always@(posedge clk)begin
if(reset)
q <= 0;
else if(q==999)
q <= 0;
else
q <= q + 1;
end
endmodule
3.2 Exams/review2015 shiftcount
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q);
always@(posedge clk)begin
if(shift_ena)
q <= {q[2:0],data};
else if(count_ena)
q <= q - 1;
else
q <= q;
end
endmodule
3.3 Exams/review2015 fsmseq
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting);
reg [2:0] state,next_state;
parameter S0=3'b000,S1=3'b001,S2=3'b011,S3=3'b010,S4=3'b110;
always@(posedge clk)begin
if(reset)
state <= S0;
else
state <= next_state;
end
always@(*)begin
case(state)
S0:begin
next_state <= data ? S1:S0;
start_shifting <= 0;
end
S1:begin
next_state <= data ? S2:S0;
start_shifting <= 0;
end
S2:begin
next_state <= data ? S2:S3;
start_shifting <= 0;
end
S3:begin
next_state <= data ? S4:S0;
start_shifting <= 0;
end
S4:begin
next_state <= S4;
start_shifting <= 1;
end
endcase
end
endmodule
3.4 Exams/review2015 fsmshift
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena);
reg state,next_state;
reg [2:0] count;
always@(posedge clk)begin
if(reset)begin
state <= 1;
count <= 1;
end
else begin
state <= next_state;
count <= count + 1;
end
end
always@(*)begin
case(state)
0:begin
next_state <= 0;
shift_ena <= 0;
end
1:begin
if(count<5) begin
next_state <= 1;
shift_ena <= 1;
end
else begin
next_state <= 0;
shift_ena <= 0;
end
end
endcase
end
endmodule
3.5 Exams/review2015 fsm
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack );
reg [3:0] state,next_state;
parameter S0 = 4'd0,S1 = 4'd1,S11 = 4'd2,S110 = 4'd3,B0 = 4'd4,B1 = 4'd5,B2 = 4'd6,B3 = 4'd7,Count = 4'd8,Wait = 4'd9;
always@(posedge clk)begin
if(reset)
state <= S0;
else
state <= next_state;
end
always@(*)begin
case(state)
S0:begin
next_state <= data ? S1:S0;
shift_ena <= 0;
end
S1:begin
next_state <= data ? S11:S0;
shift_ena <= 0;
end
S11:begin
next_state <= data ? S11:S110;
shift_ena <= 0;
end
S110:begin
next_state <= data ? B0:S0;
shift_ena <= 0;
end
B0:begin
next_state <= B1;
shift_ena <= 1;
end
B1:begin
next_state <= B2;
shift_ena <= 1;
end
B2:begin
next_state <= B3;
shift_ena <= 1;
end
B3:begin
next_state <= Count;
shift_ena <= 1;
end
Count:begin
next_state <= done_counting ? Wait:Count;
shift_ena <= 0;
end
Wait:begin
next_state <= ack ? S0:Wait;
shift_ena <= 0;
end
default:next_state <= S0;
endcase
end
assign done = (state==Wait);
assign counting = (state==Count);
endmodule
3.7 Exams/review2015 fancytimer
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack );
reg [3:0] state,next_state;
parameter S0 = 4'd0,S1 = 4'd1,S11 = 4'd2,S110 = 4'd3,B0 = 4'd4,B1 = 4'd5,B2 = 4'd6,B3 = 4'd7,Count = 4'd8,Wait = 4'd9;
reg [15:0] i;
reg [3:0] count_reg;
always@(posedge clk)begin
if(reset)
state <= S0;
else
state <= next_state;
end
always@(*)begin
case(state)
S0:begin
next_state <= data ? S1:S0;
end
S1:begin
next_state <= data ? S11:S0;
end
S11:begin
next_state <= data ? S11:S110;
end
S110:begin
next_state <= data ? B0:S0;
end
B0:begin
next_state <= B1;
count_reg[3] <= data;
end
B1:begin
next_state <= B2;
count_reg[2] <= data;
end
B2:begin
next_state <= B3;
count_reg[1] <= data;
end
B3:begin
next_state <= Count;
count_reg[0] <= data;
end
Count:begin
next_state <= (i==(count_reg+1)*1000-1) ? Wait:Count;
end
Wait:begin
next_state <= ack ? S0:Wait;
end
default:next_state <= S0;
endcase
end
always@(posedge clk)begin
if(state==Count&&i<(count_reg+1)*1000)
i = i+1;
else
i = 0;
end
reg [3:0] a;
always@(*)begin
if(i < 1000)begin
a = 4'd0;
end
else if(i >= 1000 && i < 2000)begin
a = 4'd1;
end
else if(i >= 2000 && i < 3000)begin
a = 4'd2;
end
else if(i >= 3000 && i < 4000)begin
a = 4'd3;
end
else if(i >= 4000 && i < 5000)begin
a = 4'd4;
end
else if(i >= 5000 && i < 6000)begin
a = 4'd5;
end
else if(i >= 6000 && i < 7000)begin
a = 4'd6;
end
else if(i >= 7000 && i < 8000)begin
a = 4'd7;
end
else if(i >= 8000 && i < 9000)begin
a = 4'd8;
end
else if(i >= 9000 && i < 10000)begin
a = 4'd9;
end
else if(i >= 10000 && i < 11000)begin
a = 4'd10;
end
else if(i >= 11000 && i < 12000)begin
a = 4'd11;
end
else if(i >= 12000 && i < 13000)begin
a = 4'd12;
end
else if(i >= 13000 && i < 14000)begin
a = 4'd13;
end
else if(i >= 14000 && i < 15000)begin
a = 4'd14;
end
else begin
a = 4'd15;
end
end
assign done = (state==Wait);
assign counting = (state==Count);
assign count = (state == Count) ? (count_reg - a) : 4'd0;
endmodule
3.8 Exams/review2015 fsmonehot
module top_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;
assign B3_next = state[B2];
assign S_next = ~d & state[S] | ~d & state[S1] | ~d & state[S110] | ack & state[Wait];
assign S1_next = d & state[S];
assign Count_next = state[B3] | ~done_counting & state[Count];
assign Wait_next = done_counting & state[Count] | ~ack & state[Wait];
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = state[B0] | state[B1] | state[B2] |state[B3];
endmodule
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