module dff8(clk , reset, d, q);

 input        clk;

 input        reset;

 input  [:] d;

 output [:] q;

 reg   [:] q;

 always @ (posedge clk or posedge reset)

    if(reset)

      q <= ;

    else

      q <= d;

 endmodule

 module divide2( clk , clk_o, reset);

    input     clk , reset;

    output   clk_o;

    wire in;

 reg out ;

    always @ ( posedge clk or posedge reset)

      if ( reset)

        out <= ;

          else

            out <= in;

        assign in = ~out;

        assign clk_o = out;

      endmodule