module test();

wire led_r,led_g,led_b;

reg clk = ;

always # clk <= ~clk;

led c1

(

    .clk(clk),

    .led_r(led_r),

    .led_g(led_g),

    .led_b(led_b)

);

endmodule

module led

(

    input clk,

    output reg led_r = ,

    output reg led_g = ,

    output reg led_b =

);

reg[:] cnt = ;  //计数器 

always @(posedge clk)  //

begin

    if(cnt <'d300*3)

        cnt <= cnt + ;

    else

        cnt <= ;

    case(cnt)

    'd300:

    begin

        led_r <= ;

        led_b <= ;

    end

    'd300*2:

    begin

        led_g <= ;

        led_r <= ;

    end

    'd300*3:

    begin

        led_b <= ;

        led_g <= ;

    end

    endcase

end

endmodule