【iCore1S 双核心板_FPGA】例程十五：基于I2C的ARM与FPGA通信实验
2024-08-28 02:56:35
实验现象：
核心代码：
int main(void)
{
int i,n;
char buffer[];
char i2c_buffer[]; HAL_Init();
system_clock.initialize(); led.initialize();
usart1.initialize();
i2c.initialize(); usart1.printf("Hello! I am iCore1S!\r\n"); //´®¿Ú1Êä³ö
while()
{
if(usart1.receive_ok_flag)
{ //½ÓÊÕÍê³É
usart1.receive_ok_flag = ;
for(i = ;i < ;i++)
{
buffer[i] = tolower(usart1.receive_buffer[i]);
}
n = strlen(buffer);
//±È½Ï½ÓÊÕÐÅÏ¢
if(memcmp(buffer,"ledr",strlen("ledr")) == )
{
//ºìÉ«LEDµãÁÁ
LED_RED_ON;
LED_GREEN_OFF;
LED_BLUE_OFF;
}
if(memcmp(buffer,"ledg",strlen("ledg")) == )
{
//ÂÌÉ«LEDµãÁÁ
LED_RED_OFF;
LED_GREEN_ON;
LED_BLUE_OFF;
}
if(memcmp(buffer,"ledb",strlen("ledb")) == )
{
//À¶É«LEDµãÁÁ
LED_RED_OFF;
LED_GREEN_OFF;
LED_BLUE_ON;
}
buffer[]=;//Ìí¼Ó½áÊøλ
n=strlen(buffer);
i2c.write_nbyte(0x03,0x8F,buffer,n); //i2c·¢ËÍÊý¾Ý
for(i=;i<;i++);
i2c.read_nbyte(0x03,0x0F,i2c_buffer,0x06);
usart1.printf("%s\n",i2c_buffer);//´®¿Ú1Êä³ö½ÓÊÕµ½µÄÊý¾Ý
}
}
}
module I2C(
input CLK_12M,
input SCL,
inout SDA,
output FPGA_LEDR,
output FPGA_LEDG,
output FPGA_LEDB
);
//-------------------------rst_n----------------------------//
reg rst_n;
reg [:]cnt_rst; always@(posedge CLK_12M)
begin
if(cnt_rst=='d10)
begin
rst_n <= 'd1;
cnt_rst <= 'd10;
end
else cnt_rst <= cnt_rst + 'd1;
end //-------------------------parameter------------------------//
parameter ledr = {'d108,8'd101,'d100,8'd114,'d13},
ledg = {'d108,8'd101,'d100,8'd103,'d13},
ledb = {'d108,8'd101,'d100,8'd98, 'd13},
GINGKO = {'d71,8'd73,'d78,8'd71,'d75,8'd79}; //---------------------------address------------------------//
reg [:]device_address,word_address;
reg [:]m; always@(posedge SCL or negedge rst_n)
begin
if(!rst_n)
begin
device_address <= 'd0;
word_address <= 'd0;
m <= 'd0;
tx_en <= 'd0;
rx_en <= 'd0;
end
else
begin
case(m)
'd0,5'd1,'d2,5'd3,'d4,5'd5,'d6,5'd7: //接收8位地址
begin
if(!rx_en || !tx_en)
begin
m <= m + 'd1;
device_address <= {device_address[:],SDA};
end
else m <= 'd0;
end
'd8:
begin
if(device_address=='d3 || device_address==8'd2)//识别地址
begin
m <= 'd9;
device_address <= 'd0;
end
else if(tx_ack || rx_ack)//识别应答应答
begin
m <= 'd18;
device_address <= 'd0;
end
else
begin
m <= 'd0;
end
end
'd9,5'd10,'d11,5'd12,'d13,5'd14,'d15,5'd16://接收命令
begin
m <= m + 'd1;
word_address <= {word_address[:],SDA};
end
'd17:
begin
if(word_address == 'h8f)//判断接收命令
begin
rx_en <= 'd1;
device_address <= 'hff;
word_address <= 'd0;
end
else if(word_address == 'h0f)//判断发送命令
begin
tx_en <= 'd1;
word_address <= 'd0;
end
else if(tx_ack)
begin
tx_en <= 'd0;
m <= 'd0;
end
else if(rx_ack)
begin
rx_en <= 'd0;
m <= 'd0;
end
else m <= 'd17;
end
'd18:
begin
m <= 'd0;
end
endcase
end
end
//-----------------------------rx---------------------------//
//接收数据
reg [:]data_in;
reg [:]data;
reg [:]i;
reg rx_en;
reg rx_ack; always@(posedge SCL or negedge rst_n)
begin
if(!rst_n)
begin
data_in <= 'd0;
data <= 'd0;
i <= 'd0;
rx_ack <= 'd0;
end
else if(rx_en)
begin
case(i)
'd0,5'd1,'d2,5'd3,'d4,5'd5,'d6,5'd7://接收8位数据
begin
i <= i + 'd1;
rx_ack <= 'd0;
data_in <= {data_in[:],SDA};
end
'd8:
begin
if(data_in[:]=='h0d)//判断结束为
begin
i <= 'd9;
rx_ack <= 'd1;
data <= data_in;
end
else i <= 'd0;
end
'd9:
begin
i <= 'd0;
rx_ack <= 'd0;
end
default:
begin
i <= 'd0;
end
endcase
end
end //----------------------------data--------------------------//
//对比接收数据
reg [:]led; always@(posedge CLK_12M or negedge rst_n)
begin
if(!rst_n)
begin
led <= 'b111;
end
else
begin
case(data[:])
ledr: led <= 'b011;//红灯亮
ledg: led <= 'b101;//绿灯亮
ledb: led <= 'b110;//蓝灯亮
default:led <= 'b111;//都不亮
endcase
end
end assign {FPGA_LEDR,FPGA_LEDG,FPGA_LEDB} = led; //-----------------------------tx---------------------------//
//发送数据
reg [:]data_out;
reg [:]j;
reg [:]tx_cnt;
reg tx_ack;
reg tx_en;
reg sda; always@(posedge SCL or negedge rst_n)
begin
if(!rst_n)
begin
data_out <= GINGKO;
j <= 'd0;
tx_ack <= 'd0;
tx_cnt <= 'd0;
sda <= 'd1;
end
else
begin
case(j)
'd0,4'd1,'d2,4'd3,'d4,4'd5,'d6,4'd7://发送8位书籍
begin
if(tx_en)
begin
j <= j + 'd1;
{sda,data_out[:]} <= data_out;
tx_ack <= 'd0;
end
end
'd8:
begin //发送6次，8位数据（GINGKO）
if(tx_cnt =='d5)
begin
j <= j + 'd1;
tx_ack <= 'd1;
tx_cnt <= 'd0;
end
else
begin
j <= 'd0;
tx_cnt <= tx_cnt + 'd1;
tx_ack <= 'd0;
end
end
'd9:
begin
j <= 'd0;
tx_ack <= 'd0;
data_out <= GINGKO;
end
default:
begin
j <= 'd0;
tx_ack <= 'd0;
data_out <= GINGKO;
end
endcase
end
end assign SDA = (j>='d1 && j<=4'd8)? sda : 'dz; //--------------------------endmodule-----------------------//
endmodule
实验方法及指导书:
链接：http://pan.baidu.com/s/1hs8ErAW 密码：wven
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