`timescale 1ns / 1ps

 module gray_adder

 #(parameter length = )

 (

     input clk,

     input rstn,

     input inc,

     output [length-:] Gray

     );

 reg [length-:] Gray_reg;

 reg [length-:] Gray_next_reg;

 reg [length-:] Bin_reg;

 reg [length-:] Bin_next_reg;

 integer i;

 always @(posedge clk or negedge rstn) begin

     if(!rstn) begin

         Gray_reg <= ;

     end

     else begin

         Gray_reg <= Gray_next_reg;

     end

 end

 always @(*) begin

     Bin_reg[length-] = Gray_reg[length-];    // 格雷码转二进制码

     for(i=length-;i>=;i=i-)

         Bin_reg[i] = Bin_reg[i+]^Gray_reg[i];

     Bin_next_reg = Bin_reg + inc;              // 二进制码加1

     Gray_next_reg = (Bin_next_reg>>)^Bin_next_reg;   // 二进制码转回格雷码

 end

 assign Gray = Gray_reg;

 endmodule