library  IEEE;

use  ieee.std_logic_1164.all;

--!  1)  端口定义

entity  <entity_name> is

port

(

    DIN      :  in  <data_type>;

    RST      :  in  std_logic;

    CLK      :  in  std_logic;

    DOUT   :  out  <data_type>

);

end  <entity_name>;

--!  2)  状态定义

architecture  <arch_name>  of  <entity_name>  is

type  state  is (IDLE, ST1, ST2, ...);

signal  c_state, n_state :  state;

begin

--！ 3) 时序逻辑

pfsmsyn:  process (rst, clk)

begin

  if (rst = '') then

     c_state <= IDLE;

  elsif (clk'event and clk='') then

     c_state <= n_state;

  endif;

end process;

--!  4) 组合逻辑

pfsmlogic: process (din, c_state)

begin

  case  c_state  is

    when  IDLE =>

        if (din = ...) then

            dout <= <value>;    -- 输出

            c_state <= state1;  -- 状态

        else ...

        end if;

    when  ST1 =>

        ...  ...

        ...  ...

        ...  ...

    when others =>

        ...  ...

  end case;

end process;

end  <arch_name>;

// 1) 端口声明

module fsm(clk, rst, ctrl, dout);

  input  clk, rst, ctrl;

  output  [n-:]  dout;  // n 取决于输出值的位数

  reg [n-:]  dout;

// 2) 状态定义

  parameter  IDLE = , ST1 = , ST2 = , ST3 = , ....;

  reg [m-:]  c_state, n_state;  // m 取决于‘“状态”数量的位数

// 3) 时序逻辑

always @ (posedge clk or posedge rst)

begin: SEQ

  if (rst)

    c_state = IDLE;

  else

    c_state = n_state;

end

// 4) 组合逻辑

module @ (ctrl or c_state)

begin: COMB

  case (c_state)

    IDLE: begin

              dout = <value0>;

              n_state = ST1;

            end

    ST1: begin

              dout = <value1>;

               n_state = ST2;

            end

     ST2:

            . . .  . . .

            . . .  . . .

            . . .  . . .

   endcase

end

endmodule