---

先写好一个top.sv

查看代码

// 导入VCS或者Modelsim自带的UVM库和宏

`include "uvm_macros.svh"

import uvm_pkg::*;

// 下面这些sv都是接下来要写的

`include "driver.sv"

`include "monitor.sv"

`include "agent.sv"

`include "env.sv"

`include "test.sv"

module top;

	initial

		run_test();

endmodule

再把test.sv写好。

每个phase都只有简单地打印信息，方便查看各个phase执行的顺序

查看代码

class test1 extends uvm_test;

	`uvm_component_utils(test1)

	env t_env;

	function new(string name = "test1", uvm_component parent = null);

		super.new(name, parent);

	endfunction: new

	function void build_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Build", UVM_LOW);

		t_env = env::type_id::create("t_env", this);

	endfunction: build_phase

	function void connect_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Connect", UVM_LOW);

	endfunction

	function void end_of_elaboration_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "End_of_elaboration", UVM_LOW);

	endfunction

	function void start_of_simulation_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Start_of_simulation", UVM_LOW);

	endfunction

	task run_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Run", UVM_LOW);

	endtask

	task main_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Main", UVM_LOW);

	endtask

	function void extract_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Extract", UVM_LOW);

	endfunction

	function void check_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Check", UVM_LOW);

	endfunction

	function void report_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Report", UVM_LOW);

	endfunction

	function void final_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Final", UVM_LOW);

	endfunction

endclass

env.sv

class env extends uvm_env;

	`uvm_component_utils(env)

	agent ag1;

	agent ag2;

	function new(string name, uvm_component parent);

		super.new(name, parent);

	endfunction

	function void build_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Build", UVM_LOW);

		ag1 = agent::type_id::create("ag1",this);

		ag2 = agent::type_id::create("ag2",this);

	endfunction: build_phase

	function void connect_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Connect", UVM_LOW);

	endfunction

	function void end_of_elaboration_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "End_of_elaboration", UVM_LOW);

	endfunction

	function void start_of_simulation_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Start_of_simulation", UVM_LOW);

	endfunction

	task run_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Run", UVM_LOW);

	endtask

	task main_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Main", UVM_LOW);

	endtask

	function void extract_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Extract", UVM_LOW);

	endfunction

	function void check_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Check", UVM_LOW);

	endfunction

	function void report_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Report", UVM_LOW);

	endfunction

	function void final_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Final", UVM_LOW);

	endfunction

endclass

agent.sv

查看代码

class agent extends uvm_agent;

	`uvm_component_utils(agent)

	protected uvm_active_passive_enum is_active = UVM_ACTIVE;

	monitor mon;

	driver drv;

	function new(string name, uvm_component parent);

		super.new(name, parent);

	endfunction

	function void build_phase(uvm_phase phase);

		// super.build_phase(phase);

		uvm_report_info(get_full_name(), "Build", UVM_LOW);

		mon = monitor::type_id::create("mon", this);

		drv = driver::type_id::create("drv", this);

	endfunction: build_phase

	function void connect_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Connect", UVM_LOW);

	endfunction

	function void end_of_elaboration_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "End_of_elaboration", UVM_LOW);

	endfunction

	function void start_of_simulation_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Start_of_simulation", UVM_LOW);

	endfunction

	task run_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Run", UVM_LOW);

	endtask

	task main_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Main", UVM_LOW);

	endtask

	function void extract_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Extrnct", UVM_LOW);

	endfunction

	function void check_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Check", UVM_LOW);

	endfunction

	function void report_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Report", UVM_LOW);

	endfunction

	function void final_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Final", UVM_LOW);

	endfunction

endclass

driver.sv

查看代码

class driver extends uvm_driver;

	`uvm_component_utils(driver) 

	function new(string name, uvm_component parent);

		super.new(name, parent);

	endfunction

	function void build_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Build", UVM_LOW);

	endfunction: build_phase

	function void connect_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Connect", UVM_LOW);

	endfunction

	function void end_of_elaboration_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "End_of_elaboration", UVM_LOW);

	endfunction

	function void start_of_simulation_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Start_of_simulation", UVM_LOW);

	endfunction

	task run_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Run", UVM_LOW);

	endtask

	task main_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Main", UVM_LOW);

	endtask

	function void extract_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Extract", UVM_LOW);

	endfunction

	function void check_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Check", UVM_LOW);

	endfunction

	function void report_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Report", UVM_LOW);

	endfunction

	function void final_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Final", UVM_LOW);

	endfunction

endclass

monitor.sv

查看代码

class monitor extends uvm_monitor;

	`uvm_component_utils(monitor)

	function new(string name, uvm_component parent);

		super.new(name, parent);

	endfunction

	function void build_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Build", UVM_LOW);

	endfunction: build_phase

	function void connect_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Connect", UVM_LOW);

	endfunction

	function void end_of_elaboration_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "End_of_elaboration", UVM_LOW);

	endfunction

	function void start_of_simulation_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Start_of_simulation", UVM_LOW);

	endfunction

	task run_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Run", UVM_LOW);

	endtask

	task main_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Main", UVM_LOW);

	endtask

	function void extract_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Extract", UVM_LOW);

	endfunction

	function void check_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Check", UVM_LOW);

	endfunction

	function void report_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Report", UVM_LOW);

	endfunction

	function void final_phase(uvm_phase phase);

		uvm_report_info(get_full_name(), "Final", UVM_LOW);

	endfunction

endclass

---

使用Modelsim做一下测试：

ModelSim> cd <dir> // 程序所在目录

ModelSim> vlib work

ModelSim> vlog -sv -mfcu top.sv

ModelSim> vsim top +UVM_TESTNAME=test1

ModelSim> run

检查一下输出

查看代码

# Reading C:/modeltech_10.1a/tcl/vsim/pref.tcl

# //  ModelSim SE 10.1a Feb 22 2012

# //

# //  Copyright 1991-2012 Mentor Graphics Corporation

# //  All Rights Reserved.

# //

# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION

# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS

# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.

# //

cd E:/CH02_3_LAB

vlib work

vlog -sv -mfcu top.sv

# Model Technology ModelSim SE vlog 10.1a Compiler 2012.02 Feb 22 2012

# ** Note: (vlog-2286) Using implicit +incdir+C:/modeltech_10.1a/uvm-1.1a/../verilog_src/uvm-1.1a/src from import uvm_pkg

#

# ** Warning: driver.sv(1): (vlog-2181) Use of a parameterized class uvm_driver as a type creates a default specialization.

#

# -- Compiling package top_sv_unit

# -- Importing package mtiUvm.uvm_pkg (uvm-1.1a Built-in)

# ** Warning: driver.sv(1): (vlog-2181) Use of a parameterized class uvm_driver as a type creates a default specialization.

#

# -- Compiling module top

# ** Warning: driver.sv(1): (vlog-2181) Use of a parameterized class uvm_driver as a type creates a default specialization.

#

#

# Top level modules:

# 	top

vsim top +UVM_TESTNAME=test1

# vsim +UVM_TESTNAME=test1 top

# ** Note: (vsim-3812) Design is being optimized...

#

# Loading sv_std.std

# Loading mtiUvm.uvm_pkg

# Loading work.top_sv_unit(fast)

# Loading work.top(fast)

# Loading mtiUvm.questa_uvm_pkg(fast)

# Loading C:\modeltech_10.1a\uvm-1.1a\win32\uvm_dpi.dll

run

# ----------------------------------------------------------------

# UVM-1.1a

# (C) 2007-2011 Mentor Graphics Corporation

# (C) 2007-2011 Cadence Design Systems, Inc.

# (C) 2006-2011 Synopsys, Inc.

# (C) 2011      Cypress Semiconductor Corp.

# ----------------------------------------------------------------

#

#   ***********       IMPORTANT RELEASE NOTES         ************

#

#   You are using a version of the UVM library that has been compiled

#   with `UVM_NO_DEPRECATED undefined.

#   See http://www.accellera.org/activities/vip/release_notes_11a for more details.

#

#   You are using a version of the UVM library that has been compiled

#   with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.

#   See http://www.accellera.org/activities/vip/mantis3770 for more details.

#

#       (Specify +UVM_NO_RELNOTES to turn off this notice)

#

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM]  questa_uvm::init(+struct)

# UVM_INFO @ 0: reporter [RNTST] Running test test1...

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] Build

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Build

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Build

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Build

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Build

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Build

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Build

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Build

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Connect

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Connect

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Connect

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Connect

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Connect

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Connect

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Connect

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] Connect

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] End_of_elaboration

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] End_of_elaboration

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] End_of_elaboration

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] End_of_elaboration

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] End_of_elaboration

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] End_of_elaboration

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] End_of_elaboration

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] End_of_elaboration

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Start_of_simulation

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Start_of_simulation

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Start_of_simulation

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Start_of_simulation

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Start_of_simulation

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Start_of_simulation

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Start_of_simulation

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] Start_of_simulation

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] Run

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Run

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Run

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Run

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Run

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Run

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Run

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Run

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] Main

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Main

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Main

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Main

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Main

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Main

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Main

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Main

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Extract

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Extract

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Extract

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Extract

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Extract

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Extract

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Extranct

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] Extract

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Check

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Check

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Check

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Check

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Check

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Check

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Check

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] Check

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Report

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Report

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Report

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Report

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Report

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Report

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Report

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] Report

# UVM_INFO @ 0: uvm_test_top [uvm_test_top] Final

# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Final

# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Final

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Final

# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Final

# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Final

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Final

# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Final

#

# --- UVM Report Summary ---

#

# ** Report counts by severity

# UVM_INFO :   83

# UVM_WARNING :    0

# UVM_ERROR :    0

# UVM_FATAL :    0

# ** Report counts by id

# [Questa UVM]     2

# [RNTST]     1

# [uvm_test_top]    10

# [uvm_test_top.t_env]    10

# [uvm_test_top.t_env.ag1]    10

# [uvm_test_top.t_env.ag1.drv]    10

# [uvm_test_top.t_env.ag1.mon]    10

# [uvm_test_top.t_env.ag2]    10

# [uvm_test_top.t_env.ag2.drv]    10

# [uvm_test_top.t_env.ag2.mon]    10

# ** Note: $finish    : C:/modeltech_10.1a/win32/../verilog_src/uvm-1.1a/src/base/uvm_root.svh(408)

#    Time: 0 ns  Iteration: 224  Instance: /top

# 1

# Break in Task uvm_pkg/uvm_root::run_test at C:/modeltech_10.1a/win32/../verilog_src/uvm-1.1a/src/base/uvm_root.svh line 408

---

从最后的打印结果很容易了解到各个phase的执行情况是这样的：

• 除了build和final是自顶向下的，其他phase都是自下而上的。
• 并且每个块中的phase是按顺序执行的。

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