HDLBits答案——Verification: Writing Testbenches
2024-10-21 03:46:03
1 clock
module top_module ( );
reg clk;
dut U1(.clk(clk));
initial begin
clk = 0;
end
always begin
#5;
clk = ~clk;
end
endmodule
2 Tb/tb1
module top_module ( output reg A, output reg B );//
// generate input patterns here
initial begin
A = 0;
B = 0;
#10;
A = 1;
#5;
B = 1;
#5;
A = 0;
#20;
B = 0;
end
endmodule
3 Tb/and
module top_module();
reg a,b,out;
initial begin
a = 0;
b = 0;
#10;
a = 0;
b = 1;
#10;
a = 1;
b = 0;
#10;
a = 1;
b = 1;
end
andgate U1({a,b},out);
endmodule
4 Tb/tb2
module top_module();
reg clk;
reg in;
reg [2:0] s;
reg out;
q7 U1(.clk(clk), .in(in), .s(s), .out(out));
initial begin
clk = 0;
in = 0;
s = 3'd2;
#10;
in = 0;
s = 3'd6;
#10;
in = 1;
s = 3'd2;
#10;
in = 0;
s = 3'd7;
#10;
in = 1;
s = 3'd0;
#30;
in = 0;
end
always begin
#5;
clk = ~clk;
end
endmodule
5 Tb/tff
module top_module ();
reg clk,reset,t,q;
tff U1(.clk(clk),
.reset(reset),
.t(t),
.q(q));
initial begin
clk = 0;
t = 0;
reset = 0;
end
always begin
#5;
clk = ~clk;
end
initial begin
reset = 1'b0;
#3;
reset = 1'b1;
#10;
reset = 1'b0;
end
always@(posedge clk)begin
if(reset)
t = 1;
else
t = 0;
end
endmodule
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