STA之Concepts (2)

3　　Skew between signals

　　Skew is the difference in timing between two or more signals, maybe data, clock or both.

　　Clock latency is the total time it takes from the clock source to an end point.

　　Clock skew is the difference in arrival times at the end points of the clock tree.

　　Latency of a clock tree can be explicitly specified using the set_clock_latency command.

set_clock_latency 2.2 [get_clocks BZCLK]

# Both rise and fall latency is 2.2ns.

# Use options -rise and -fall if different.

　　Clock skew for a clock tree can also be implied by explicitly specifying its value using the set_clock_uncertainty command.

set_clock_uncertainty 0.250 -setup [get_clocks BZCLK]

set_clock_uncertainty 0.100 -hold [get_clocks BZCLK]

　　The set_clock_uncertainty specifies a window within which a clock edge can occur. Every real clock source has a finite amount of jitter - a window within which a clock edge can occur.

　　Figure 2-16 shows an example of a clock with a setup uncertainty of 250ps. Figure 2-16(b) shows how the uncertainty takes away from the time available for the logic to propagate to the next flip-flop stage.

4　　Timing Arcs and Unateness

　　Every cell has multiple timing arcs. 　　(uate -- 单边)

　　- Combinational logic cell, such as and, or, nand, nor, adder cell, has timing arcs from each input to each output of the cell.

　　- Sequential cell (flip-flop) has timing arc from the clock to the output and timing constraints for the data pins with respect to the clock.

5　　Min and Max timing paths

　　A max path between two end points is the path with the largest delay (also referred to as the longest path). Similarly, a min path is the path with the smallest delay (also referred to as the shortest path).

　　When a flip-flop to flip-flop path, one of the flip-flops launches the data and the other flip-flop captures the data.

　　In this case, UFF1 is referred to as the launch flip-flop, and UFF3 is referred to as the capture flip-flop.

　　The launch and capture terminology are always with reference to a flip-flop to flip-flop path. For example, UFF3 would become a launch flip-flop for the path to whatever flip-flop captures the data produced by UFF3.

6　　Clock domains

　　A clock typically feeds a number of flip-flops. The set of flip-flops being fed by one clock is called its clock domain.

　　For example, 200 flip-flops may be clocked by USBCLK and 1000 flip-flops may be fed by clock MEMCLK. Figure 2-20 depicts the flip-flops along with the clocks. In this example, we say that there are two clock domains.

　　If indeed there are data paths that cross between clock domains (see Figure2-21), a decision has to be made as to whether the paths are real or not.

　　An example of a real path is a flip-flop with a 2x speed clock driving into a flip-flop with a 1x speed clock.

　　An example of a false path is where the designer has explicitly placed clock synchronizer logic between the two clock domains. Such a path is referred to as a false path, because the clock synchronizer ensures that the data passes correctly from one domain to the next.　　　

set_false_path -from [get_clocks USBCLK] -to [get_clocks MEMCLK]

巴特西

STA之Concepts (2)

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