//主要是// 和**********部分是关键
 1 `timescale 1ns/1ns

 module tb();

                   reg  main_clk;

                   reg [:] addr;

                   reg FPGA_CS0;//FPGA cs

                   reg RD;

                   reg WR;

                   wire arm_clk;

                   wire led;

                   wire [:]data;        //*******

                   reg [:] treg_data;  //关键部分

                   integer i;            //

 assign data = treg_data;               //*****  

 STM32_FPGA u1(

                   .main_clk(main_clk),

                   .arm_clk(arm_clk),

                   .led(led),

                   .addr(addr),

                   .data(data),

                   .FPGA_CS0(FPGA_CS0),//FPGAƬ

                   .RD(RD),

                   .WR(WR)

                  );

 initial begin

     main_clk = ;

     addr = 'd0;

     FPGA_CS0 = ;

     RD = ;

     WR = ;

     i = ;

     treg_data = ;

     #

     for(i=;i<;i=i+)begin             //往FPGA寄存器写入8个随机数据

         WR =  ;

         addr = i;

         treg_data = $random;

         #

         WR = ;

         #;

     end

     treg_data ='bz;                 //写完后，treg_data 与 data 断开

     #

     for(i=;i<;i=i+)begin           //从FPGA 寄存器读出8个数据

         FPGA_CS0 = ;

         RD = ;

         addr = i;

         #;

     end

     FPGA_CS0 = ;

     RD = ;

 end

 always # main_clk = ~main_clk;

 endmodule 

 module STM32_FPGA(

                       input  main_clk,

                       output arm_clk,

                       output led,

                       input [:] addr,

                       inout[:] data,

                       input FPGA_CS0,//FPGA片选

                       input RD,

                       input WR

                      );

 wire clk;

 pll_50M    pll_50M_inst (

                                 .inclk0 ( main_clk ),//25M

                                 .c0 ( clk ),         //50M

                                 .c1 ( arm_clk )      //8M

                              );

 reg [:] cnt = ;

 always @(posedge clk)

   cnt <= cnt + 'b1;             

 assign led = cnt[];

 //AWE的上升沿，将数据写入FPGA寄存器

 reg [:] ARM_FPGA_REG0;

 reg [:] ARM_FPGA_REG1;

 reg [:] ARM_FPGA_REG2;

 reg [:] ARM_FPGA_REG3;

 reg [:] ARM_FPGA_REG4;

 reg [:] ARM_FPGA_REG5;

 reg [:] ARM_FPGA_REG6;

 reg [:] ARM_FPGA_REG7;                     

 wire rd_en = ~FPGA_CS0 && ~RD;

 reg [:] data_reg;

 //always @(posedge clk) //DSP读操作,The sampling point of DSP reading is the risging edge of AWE!

 always @(*)

 begin

    if(rd_en)

      begin

         case(addr[:])

          'd0   :  data_reg <= ARM_FPGA_REG0;

          'd1   :  data_reg <= ARM_FPGA_REG1;

          'd2   :  data_reg <= ARM_FPGA_REG2;

          'd3   :  data_reg <= ARM_FPGA_REG3;

          'd4   :  data_reg <= ARM_FPGA_REG4;

          'd5   :  data_reg <= ARM_FPGA_REG5;

          'd6   :  data_reg <= ARM_FPGA_REG6;

          'd7   :  data_reg <= ARM_FPGA_REG7;

          default:  data_reg<= 'hzzzz;

         endcase

      end

    else      data_reg<= 'hzzzz;

 end                                                           

 /* AWE下降沿DSP的数据写入FPGA，即sampling point */                     

 reg WR_tmp1;

 reg WR_tmp2;

 always @(posedge clk)

 begin

     WR_tmp1 <= WR;

     WR_tmp2 <= WR_tmp1;

 end                     

 wire WR_RISING = WR_tmp2 && ~WR_tmp1;//与clk同步         

 always @(*)

 begin

   if(WR_RISING)

      begin

         case(addr[:])

          'd0   :  ARM_FPGA_REG0 <= data;

          'd1   :  ARM_FPGA_REG1 <= data;

          'd2   :  ARM_FPGA_REG2 <= data;

          'd3   :  ARM_FPGA_REG3 <= data;

          'd4   :  ARM_FPGA_REG4 <= data;

          'd5   :  ARM_FPGA_REG5 <= data;

          'd6   :  ARM_FPGA_REG6 <= data;

          'd7   :  ARM_FPGA_REG7 <= data;

          default:  ;

         endcase

      end

   else begin

     ARM_FPGA_REG0 <= ARM_FPGA_REG0;

     ARM_FPGA_REG1 <= ARM_FPGA_REG1;

     ARM_FPGA_REG2 <= ARM_FPGA_REG2;

     ARM_FPGA_REG3 <= ARM_FPGA_REG3;

     ARM_FPGA_REG4 <= ARM_FPGA_REG4;

     ARM_FPGA_REG5 <= ARM_FPGA_REG5;

     ARM_FPGA_REG6 <= ARM_FPGA_REG6;

     ARM_FPGA_REG7 <= ARM_FPGA_REG7;

   end

 end

  // assign data = rd_en ? data_reg : 16'hzzzz;

 assign data = data_reg;  //可以用三目运算，但根据54行到68行逻辑判断，没有必要

 endmodule