HDLBits答案——Verification: Reading Simulations
2024-10-20 16:07:58
1 Finding bugs in code
1.1 Bugs mux2
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out );
assign out = sel ? a:b;
endmodule
1.2 Bugs nand3
module top_module (input a, input b, input c, output out);//
wire out_0;
andgate inst1 (out_0, a, b, c, 1'b1 , 1'b1);
assign out = ~out_0;
endmodule
1.3 Bugs mux4
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out ); //
wire [7:0] mux0;
wire [7:0] mux1;
mux2 U1 ( sel[0], a, b, mux0 );
mux2 U2 ( sel[0], c, d, mux1 );
mux2 U3 ( sel[1], mux0, mux1, out );
endmodule
1.4 Bugs addsubz
// synthesis verilog_input_version verilog_2001
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);//
always @(*) begin
case (do_sub)
0: out <= a+b;
1: out <= a-b;
endcase
if (out==0)
result_is_zero = 1;
else
result_is_zero = 0;
end
endmodule
1.5 Bugs case
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid );//
always @(*)begin
case (code)
8'h45:begin
out <= 0;
valid <= 1;
end
8'h16:begin
out <= 1;
valid <= 1;
end
8'h1e:begin
out <= 2;
valid <= 1;
end
8'h26:begin
out <= 3;
valid <= 1;
end
8'h25:begin
out <= 4;
valid <= 1;
end
8'h2e:begin
out <= 5;
valid <= 1;
end
8'h36:begin
out <= 6;
valid <= 1;
end
8'h3d:begin
out <= 7;
valid <= 1;
end
8'h3e:begin
out <= 8;
valid <= 1;
end
8'h46:begin
out <= 9;
valid <= 1;
end
default:begin
valid <= 0;
out <= 0;
end
endcase
end
endmodule
2 Build a circuit from a simulationwaveform
2.1 Sim/circuit1
module top_module (
input a,
input b,
output q );//
assign q = a&b; // Fix me
endmodule
2.2 Sim/circuit2
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = ~a & ~b & ~c & ~d | ~a & ~b & c & d | ~a & b & ~c & d | ~a & b & c & ~d |
a & b & ~c & ~d | a & b & c & d | a & ~b & ~c & d | a & ~b & c & ~d;
endmodule
2.3 Sim/circuit3
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b & d | b & c | a & d | a & c; // Fix me
endmodule
2.4 Sim/circuit4
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b|c; // Fix me
endmodule
2.5 Sim/circuit5
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q );
always@(*)begin
case(c)
4'd0:q<=b;
4'd1:q<=e;
4'd2:q<=a;
4'd3:q<=d;
default:q<=4'hf;
endcase
end
endmodule
2.6 Sim/circuit6
module top_module (
input [2:0] a,
output [15:0] q );
always@(*)begin
case(a)
3'd0:q<=16'h1232;
3'd1:q<=16'haee0;
3'd2:q<=16'h27d4;
3'd3:q<=16'h5a0e;
3'd4:q<=16'h2066;
3'd5:q<=16'h64ce;
3'd6:q<=16'hc526;
3'd7:q<=16'h2f19;
endcase
end
endmodule
2.7 Sim/circuit7
module top_module (
input clk,
input a,
output q );
always@(posedge clk)begin
q <= ~a;
end
endmodule
2.8 Sim/circuit8
module top_module (
input clock,
input a,
output p,
output q );
always@(*)begin
if(clock)
p <= a;
else
p <= p;
end
always@(negedge clock)begin
q <= p;
end
endmodule
2.9 Sim/circuit9
module top_module (
input clk,
input a,
output [3:0] q );
always@(posedge clk)begin
if(a)begin
q <= 4'd4;
end
else if(q == 4'd6)begin
q <= 4'd0;
end
else begin
q <= q + 1'b1;
end
end
endmodule
2.10 Sim/circuit10
module top_module (
input clk,
input a,
input b,
output q,
output state );
always @(posedge clk) state <= state ? a|b : a&b;
assign q = a^b^state;
endmodule
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