//##################################################################################################

 //  Project     : AMBA AHB RAM

 //  Author      : Lyu Yang

 //  Date        : 2020-05-10

 //  Description : AHB RAM

 //##################################################################################################

 module ahb_ram (

     input   wire                hclk        ,

     input   wire                hreset_n    ,

     input   wire                hsel        ,

     input   wire    [:]       htrans      ,

     input   wire                hwrite      ,

     input   wire    [:]       hsize       ,

     input   wire    [:]      haddr       ,

     input   wire    [:]      hwdata      ,

     input   wire                hready_in   ,

     output  reg     [:]      hrdata      ,

     output                      hready_out  ,

     output  wire    [:]       hresp

 );

 localparam      MEM_SIZE = ;

 wire            hbus_ena;

 reg             hbus_ena_d;

 reg     [:]   mem_wstrb;

 reg     [:]  mem [:MEM_SIZE-];

 // Memory Init

 initial $readmemh("../../frw/app_test.txt", mem);

 // AHB response always OKAY

 assign hresp = 'h0;

 assign hready_out = 'b1;

 assign hbus_ena = hsel & hready_in & htrans[];

 always @(posedge hclk, negedge hreset_n)

     if(~hreset_n)

         hbus_ena_d <= 'b0;

     else

         hbus_ena_d <= hbus_ena;

 always @(posedge hclk, negedge hreset_n)

     if(~hreset_n)

         mem_wstrb <= 'h0;

     else if(hbus_ena & hwrite) begin

         case(hsize)

             'b000: begin

                 case(haddr[:])

                     'b00: mem_wstrb <= 4'b0001;

                     'b01: mem_wstrb <= 4'b0010;

                     'b10: mem_wstrb <= 4'b0100;

                     'b11: mem_wstrb <= 4'b1000;

                 endcase

             end

             'b001: begin

                 case(haddr[])

                     'b0: mem_wstrb <= 4'b0011;

                     'b1: mem_wstrb <= 4'b1100;

                 endcase

             end

             'b010: begin

                 mem_wstrb <= 'b1111;

             end

             default: begin

                 mem_wstrb <= 'b0000;

             end

         endcase

     end

     else begin

         mem_wstrb <= 'b0000;

     end

 always @(posedge hclk)

     if(hbus_ena_d) begin

         if(mem_wstrb[])

             mem[haddr[:]][ : ] <= hwdata[ : ];

         if(mem_wstrb[])

             mem[haddr[:]][: ] <= hwdata[: ];

         if(mem_wstrb[])

             mem[haddr[:]][:] <= hwdata[:];

         if(mem_wstrb[])

             mem[haddr[:]][:] <= hwdata[:];

     end

 always @(posedge hclk)

     if(hbus_ena)

         hrdata <= mem[haddr[:]];

 endmodule