/***UART transmit function by xu ***/

 display_addr_dat:

     ldr r0,[r0]

     ldr r1,=0xE2900020 

     ldr r2,=0x30

     str r2,[r1]     @UTXH0=''

     ldr r2,=0x78

     str r2,[r1]     @UTXH0='x'

     ldr r3,=

 display_loop_count:

     lsr r2,r0,r3    @logical shift right  bit

     and r2,r2,#0xF     

     cmp r2,#      @cmp r2 is mi or pl

     addmi r2,r2,#0x30  @r2 is ----

     addpl r2,r2,#0x37  @r2 is A----F

     str r2,[r1]

     sub r3,r3,#

     cmp r3,#

     bpl display_loop_count

     ldr r2,=0xa

     str r2,[r1]     @UTXH0='\r'

     ldr r2,=0xd

     str r2,[r1]     @UTXH0='\n'

     mov pc, lr

 /*** ddrmem initialze by xu***/

 .globl ddrmem_init

 ddrmem_init:

 #define ELFIN_GPIO_BASE            0xE0200000

 #define APB_DMC_0_BASE            0xF0000000

 #define DMC_CONCONTROL             0x00

 #define DMC_MEMCONTROL             0x04

 #define DMC_MEMCONFIG0             0x08

 #define DMC_DIRECTCMD             0x10

 #define DMC_PRECHCONFIG         0x14

 #define DMC_PHYCONTROL0         0x18

 #define DMC_PHYCONTROL1         0x1C

 #define DMC_RESERVED             0x20

 #define DMC_PWRDNCONFIG         0x28

 #define DMC_TIMINGAREF             0x30

 #define DMC_TIMINGROW             0x34

 #define DMC_TIMINGDATA             0x38

 #define DMC_TIMINGPOWER         0x3C

 #define DMC_PHYSTATUS             0x40

 #define DMC_CHIP0STATUS         0x48

 #define DMC_AREFSTATUS             0x50

 #define DMC_MRSTATUS             0x54

 #define DMC_PHYTEST0             0x58

     //初始化PHY DLL

     ldr r0, =APB_DMC_0_BASE

     //step 2 set PhyControl0.ctrl_start_point PhyControl0.ctrl_inc PhyControl0.ctrl_dll_on bit field to 1

     ldr r1, =0x0010100A

     str r1, [r0,#DMC_PHYCONTROL0]

     //step 3 set PhyControl1.ctrl_shiftc PhyControl1.ctrl_ctrl_offsetc

     ldr r1, =0x00000086

     str r1, [r0,#DMC_PHYCONTROL1]

     //step 4 set PhyControl0.ctrl_start bit-field to 1 DLL on

     ldr r1, =0x0010100B

     str r1, [r0,#DMC_PHYCONTROL0]

 find_lock_val:

     //step 11 loop until DLL is locked

     ldr r1, [r0,#DMC_PHYSTATUS]

     and r2, r1,#0x7

     cmp r2, #0x7

     bne find_lock_val

     //setp 12 Force value looking

     and r1, #0x3fc0

     mov r2, r1, LSL #

     orr r2, r2, #0x100000

     orr r2, r2, #0x1000

     orr r1, r2, #0xB

     str r1, [r0,#DMC_PHYCONTROL0]

     //初始化DMC0

     //step 5 set ConControl

     ldr r1, =0x0FFF1010

     str r1, [r0,#DMC_CONCONTROL]

     //step 6 set MemControl

     ldr r1, =0x00202400

     str r1, [r0,#DMC_MEMCONTROL]

     //step 7 set MemConfig0 512M config,8 banks

     ldr r1, =0x20E00323

     str r1, [r0,#DMC_MEMCONFIG0]

     //step 8/1 set PrechConfig

     ldr r1, =0xFF000000

     str r1, [r0,#DMC_PRECHCONFIG]

     //step 9/1 set TimingAref t_refi=7.5us * 133MHz=1038(0x40E)

     ldr r1, =0x0000040E

     str r1, [r0,#DMC_TIMINGAREF]

     //step 9/2 set TimingRow tRAS=45ns tRC=60ns tRCD=15ns tRP=15ns tRRD=7.5ns tRFC=127.5ns

     ldr r1, =0x11122206

     str r1, [r0,#DMC_TIMINGROW]

     //step 9/3 set TimingData tWTR=7.5ns tWR=15ns tRTP=7.5ns cl=4

     ldr r1, =0x12140000

     str r1, [r0,#DMC_TIMINGDATA]

     //step 9/4 set TimingPower t_mrd>=tMRD=2nCK t_cke<=tCKE=3nCK t_xp>=tXP=2nCK tXSRD=200ns tFAW=35ns

     ldr r1, =0x05DC0343

     str r1, [r0,#DMC_TIMINGPOWER]

     //初始化DDR2 DRAM

     //step 14 lssue a "NOP" for DirectCmd and hold CKE to high level

     ldr r1, =0x07000000

     str r1, [r0,#DMC_DIRECTCMD]

     //step 16 lssue a "PALL" for DirectCmd

     ldr r1, =0x01000000

     str r1, [r0,#DMC_DIRECTCMD]

     //step 17 lssue an "EMRS2" for DirectCmd

     ldr r1, =0x00020000

     str r1, [r0,#DMC_DIRECTCMD]

     //step 18 lssue an "EMRS3" for DirectCmd

     ldr r1, =0x00030000

     str r1, [r0,#DMC_DIRECTCMD]

     //step 19 lssue an "EMRS" for DirectCmd and enable DLLs enable DQS

     ldr r1, =0x00010000

     str r1, [r0,#DMC_DIRECTCMD]

     //step 20 lssue a "MRS" for DirectCmd and reset DLL

     ldr r1, =0x00000542

     str r1, [r0,#DMC_DIRECTCMD]

     //step 21 lssue a "PALL" for DirectCmd

     ldr r1, =0x01000000

     str r1, [r0,#DMC_DIRECTCMD]

     //step 22 lssue two "Auto Refresh" for DirectCmd

     ldr r1, =0x05000000

     str r1,[r0,#DMC_DIRECTCMD]

     ldr r1, =0x05000000

     str r1,[r0,#DMC_DIRECTCMD]

     //step 23 lssue a "MRS" for DirectCmd and without reseting DLL

     ldr r1, =0x00000442

     str r1, [r0,#DMC_DIRECTCMD]

     //step 25 lssue an "EMRS" for DirectCmd  set OCD Calibration Default and exit OCD Calibration

     ldr r1, =0x00010380

     str r1, [r0,#DMC_DIRECTCMD]

     ldr r1, =0x00010000

     str r1, [r0,#DMC_DIRECTCMD]

     //step 27 set ConControl and turn on "auot refresh"

     ldr r1, =0x0FF01030

     str r1, [r0,#DMC_CONCONTROL]

     //step 8/2 set PwrdnConfig

     ldr r1, =0xFFFF00FF

     str r1, [r0,#DMC_PWRDNCONFIG]

     //step 28 IF power down modes is required set MemControl

     ldr r1, =0x00202400

     str r1, [r0,#DMC_MEMCONTROL]

     //putout URAT char "DDR IS OK!"

     ldr r0, =0xE2900020

     ldr r1, =0x44    @UTH='D'

     str r1, [r0]

     ldr r1, =0x44

     str r1, [r0]     @UTH='D'

     ldr r1, =0x52

     str r1, [r0]     @UTH='R'

     ldr r1, =0x20

     str r1, [r0]     @UTH=' '

     ldr r1, =0x49

     str r1, [r0]     @UTH='I'

     ldr r1, =0x53

     str r1, [r0]     @UTH='S'

     ldr r1, =0x20

     str r1, [r0]     @UTH=' '

     ldr r1, =0x4f

     str r1, [r0]     @UTH='O'

     ldr r1, =0x4b

     str r1, [r0]     @UTH='K'

     ldr r1, =0x21

     str r1, [r0]    @UTH='!'

     ldr r1,    =0xa

     str r1,    [r0]     @UTXH0='\r'

     ldr r1,    =0xd

     str r1,    [r0]     @UTXH0='\n'

     mov pc, lr