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-- Your use of Altera Corporation's design tools, logic functions

-- and other software and tools, and its AMPP partner logic

-- functions, and any output files from any of the foregoing

-- (including device programming or simulation files), and any

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-- to the terms and conditions of the Altera Program License

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-- without limitation, that your use is for the sole purpose of

-- programming logic devices manufactured by Altera and sold by

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-- applicable agreement for further details.

-- ***************************************************************************

-- This file contains a Vhdl test bench template that is freely editable to

-- suit user's needs .Comments are provided in each section to help the user

-- fill out necessary details.

-- ***************************************************************************

-- Generated on "12/01/2015 20:34:30"

-- Vhdl Test Bench template for design  :  f_adder

--

-- Simulation tool : ModelSim-Altera (VHDL)

-- 

LIBRARY ieee;

USE ieee.std_logic_1164.all;                                

ENTITY f_adder_vhd_tst IS

END f_adder_vhd_tst;

ARCHITECTURE f_adder_arch OF f_adder_vhd_tst IS

-- constants

-- signals

SIGNAL ain : STD_LOGIC;

SIGNAL bin : STD_LOGIC;

SIGNAL cin : STD_LOGIC;

SIGNAL cout : STD_LOGIC;

SIGNAL sum : STD_LOGIC;  --所要信号的声明

COMPONENT f_adder

    PORT (

    ain : IN STD_LOGIC;

    bin : IN STD_LOGIC;

    cin : IN STD_LOGIC;

    cout : OUT STD_LOGIC;

    sum : OUT STD_LOGIC

    );

END COMPONENT;

BEGIN

    i1 : f_adder

    PORT MAP (

-- list connections between master ports and signals

    ain => ain,

    bin => bin,

    cin => cin,

    cout => cout,

    sum => sum

    );

init : PROCESS

-- variable declarations

BEGIN

        -- code that executes only once

WAIT;

END PROCESS init;

always : PROCESS

-- optional sensitivity list

-- (        )

-- variable declarations

BEGIN

        -- code executes for every event on sensitivity list

WAIT;

END PROCESS always;

END f_adder_arch;

SIGNAL ain : STD_LOGIC :='';

SIGNAL bin : STD_LOGIC :='';

SIGNAL cin : STD_LOGIC :='';

SIGNAL cout : STD_LOGIC;

SIGNAL sum : STD_LOGIC;