systemverilog 之interface/timing region/program

1.connecting the testbench and the design

2.verilog connection review

3.systemverilog interfaces

4.stimulus timing

5.clocking blocks

6.timing regions

7.program block

Connecting Testbench and Design

1.use the conventional verilog module ports

implicit .* port connections

2.use interface and then instance

interface arb_if(input bit clk);

logic [1:0] grant,request;

logic reset;

endinterface

module top;

bit clk;

always #5 clk =~clk;

arb_if arbif (clk);

arb a1(arbif);

test t1(arbif);

endmodule:top

module tb(arb_if arbif);

…

initial begin

@(posedge arbif.clk);

arbif.request <= 2’b01;

$display(“@%0t:Drove req =01”,$time);

repeat(2) @(posedge arbif.clk)

if(arbif.grant != 2’b01)

$display(“@0d:a1:grant !=2’b01”,$time);

$finish;

end

endmodule:test

HOW connecting interfaces and ports

<port_name>.<internal_interface_signal_name>

interface modport

1.modport provide a means to define different views of the interface signal

2.modport is an abbreviation for module port

3.an interface can have any number of modport definitions

4.the modport declaration only defines whether the connecting module sees a signal as an input output or bidirectional

STIMULUS TIMING

The timing between the testbench and the design

should be maintained to avoid race contiditions

clocking blocks ===> synchronous signals

default input #1step output #0

1.synchronize to active clock edge specified in clocking block

@arbif.cb;

repeat(3)@arbif.cb;

2.synchronize to any edge of signal

@arbif.cb.grant;

@(posedge arbif.cb.grant);

wait(arbif.cb.grant ==1);

3.wait for N clock cycles with ##n –blocking statment

##2 arbif.cb.request <=0; //wait 2 cycles then assign

3.clocking block signals are referenced by pre-pending the clocking block name to the signal:

all dirves must use non-blocking assigment

arbif.cb.request <= 1; //dirve

value = arbif.cb.grant ; // sample

4.clocking blocks overview

(1) use in the interface just for testbench

(2)benefits:

synchronous timing domains

race-free if input skew > 0

drive signals always at right time

(3)functionality:

can contain multiple clocking blocks

default input #1step output #0

巴特西

systemverilog 之interface/timing region/program

最新文章

热门文章