static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;

 /*

  * Adjust the PMD section entries according to the CPU in use.

  */

 static void __init build_mem_type_table(void)

 {

     struct cachepolicy *cp;

     unsigned int cr = get_cr();

     unsigned int user_pgprot, kern_pgprot, vecs_pgprot;

     int cpu_arch = cpu_architecture();

     int i;

     /*

      * Mark the device areas according to the CPU/architecture.

      */

     /*

      * Mark device regions on ARMv6+ as execute-never

      * to prevent speculative instruction fetches.

      */

     mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;

     mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;

     mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;

     mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;

     /*

      * Now deal with the memory-type mappings

      */

      /*

      {

         .policy        = "writeback",

         .cr_mask    = 0,

         .pmd        = PMD_SECT_WB,

         .pte        = L_PTE_MT_WRITEBACK,

     }

      */

     cp = &cache_policies[cachepolicy];

     vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;

     /*

      * Only use write-through for non-SMP systems

      */

      /*

      {

         .policy        = "writethrough",

         .cr_mask    = 0,

         .pmd        = PMD_SECT_WT,

         .pte        = L_PTE_MT_WRITETHROUGH,

     }

      */

     vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;

     /*

      * ARMv6 and above have extended page tables.

      */

     if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {

         /*

          * Mark cache clean areas and XIP ROM read only

          * from SVC mode and no access from userspace.

          */

         mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;

         mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;

         mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;

     }

     /*

      * Non-cacheable Normal - intended for memory areas that must

      * not cause dirty cache line writebacks when used

      */

     /* For both ARMv6 and non-TEX-remapping ARMv7 */

     mem_types[MT_MEMORY_NONCACHED].prot_sect |=

     PMD_SECT_TEX();

     for (i = ; i < ; i++) {

         unsigned long v = pgprot_val(protection_map[i]);

         protection_map[i] = __pgprot(v | user_pgprot);

     }

     mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;

     mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;

     pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);

     pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |

                  L_PTE_DIRTY | L_PTE_WRITE |

                  L_PTE_EXEC | kern_pgprot);

     mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;

     mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;

     mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;

     mem_types[MT_ROM].prot_sect |= cp->pmd;

     switch (cp->pmd) {

     case PMD_SECT_WT:

         mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;

         break;

     case PMD_SECT_WB:

     case PMD_SECT_WBWA:

         mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;

         break;

     }

     printk("Memory policy: ECC %sabled, Data cache %s\n",

         ecc_mask ? "en" : "dis", cp->policy);

     for (i = ; i < ARRAY_SIZE(mem_types); i++) {

         struct mem_type *t = &mem_types[i];

         if (t->prot_l1)

             t->prot_l1 |= PMD_DOMAIN(t->domain);

         if (t->prot_sect)

             t->prot_sect |= PMD_DOMAIN(t->domain);

     }

 }