基于Verilog的以2为底取对数函数log2(x)

参考资料：xilinx AXI4 Stream Peripherals 源码

//************************************************************************

Verilog中函数使用方法这里不再赘述，只给出函数原型及其调用方式。

//************************************************************************

//function called clogb2 that returns an integer which has the

//value of the ceiling of the log base 2.

function integer clogb2 (input integer bit_depth);

begin

for(clogb2=0; bit_depth>0; clogb2=clogb2+1)

bit_depth = bit_depth>>1;

end

endfunction

//************************************************************************

localparam WIDTH_SRL = 32;

localparam WIDTH_CNT = clogb2(WIDTH_SRL/8-1);

转载：http://www.eefocus.com/mastershifu2015/blog/16-08/389919_64de0.html

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