​

module edge_detect(

                   input    clk,

                   input    rst_n,

                   input    data_in,

                   output   raising_edge_detect,         //上升沿标志位

                   output   falling_edge_detect,         //下降沿标志位

                   output   double_edge_detect           //双边沿标志位

 );

//reg define

  reg   data_in_d1;        //寄存器d1

  reg   data_in_d2;        //寄存器d2

assign  raising_edge_detect = data_in_d1  & (~data_in_d2);   //上升沿，标志位置1

assign  falling_edge_detect = ~data_in_d1 &  data_in_d2;     //下降沿，标志位置1

assign  double_edge_detect  = data_in_d1 ^ data_in_d2;       //双边沿，标志位置1

always @ (posedge clk or negedge rst_n)begin

    if(!rst_n)begin

       data_in_d1 <= 'b0;

       data_in_d2 <= 'b0;

    end

    else begin

       data_in_d1 <= data_in;             //这里需注意data_in 采集数据的电平状态，延时了2个时钟

       data_in_d2 <= data_in_d1;            周期才到寄存器data_in_d2

    end

end 

endmodule

​