COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE NINTH EDITION

In this section, we look at some of the general characteristics of and the motivation
for a reduced instruction set architecture. Specific examples will be seen later in
this chapter. We begin with a discussion of motivations for contemporary complex
instruction set architectures.

Why CISC
We have noted the trend to richer instruction sets, which include a larger number
of instructions and more complex instructions. Two principal reasons have moti-
vated this trend: a desire to simplify compilers and a desire to improve performance.
Underlying both of these reasons was the shift to HLLs on the part of programmers;
architects attempted to design machines that provided better support for HLLs.

It is not the intent of this chapter to say that the CISC designers took the
wrong direction. Indeed, because technology continues to evolve and because archi-
tectures exist along a spectrum rather than in two neat categories, a black-and-white
assessment is unlikely ever to emerge. Thus, the comments that follow are simply
meant to point out some of the potential pitfalls in the CISC approach and to pro-
vide some understanding of the motivation of the RISC adherents.

The first of the reasons cited, compiler simplification, seems obvious, but it
is not. The task of the compiler writer is to build a compiler that generates good
(fast, small, fast and small) sequences of machine instructions for HLL programs
(i.e., the compiler views individual HLL statements in the context of surrounding
HLL statements). If there are machine instructions that resemble HLL statements,
this task is simplified. This reasoning has been disputed by the RISC researchers
([HENN82], [RADI83], [PATT82b]). They have found that complex machine
instructions are often hard to exploit because the compiler must find those cases
that exactly fit the construct. The task of optimizing the generated code to mini-
mize code size, reduce instruction execution count, and enhance pipelining is much
more difficult with a complex instruction set. As evidence of this, studies cited
earlier in this chapter indicate that most of the instructions in a compiled program
are the relatively simple ones.

The other major reason cited is the expectation that a CISC will yield smaller,
faster programs. Let us examine both aspects of this assertion: that programs will be
smaller and that they will execute faster.
There are two advantages to smaller programs. First, because the program
takes up less memory, there is a savings in that resource. With memory today being
so inexpensive, this potential advantage is no longer compelling. More important,
smaller programs should improve performance, and this will happen in three ways.
First, fewer instructions means fewer instruction bytes to be fetched. Second, in a
paging environment, smaller programs occupy fewer pages, reducing page faults.
Third, more instructions fit in cache(s).

https://www.kancloud.cn/wintry/python3/742475

CPU体系架构

RISC与CISC

Reduced Instruction Set Computer
Complex Instruction Set Computer

RISC(精简指令集计算机)和CISC(复杂指令集计算机)是当前CPU的两种架构。
它们的区别在于不同的CPU设计理念和方法。

早期的CPU全部是CISC架构，它的设计目的是要用最少的机器语言指令来完成所需的计算任务。
比如对于乘法运算，在CISC架构的CPU上，您可能需要这样一条指令：
MUL ADDRA, ADDRB
就可以将ADDRA和ADDRB中的数相乘并将结果储存在ADDRA中。
将ADDRA, ADDRB中的数据读入寄存器，
相乘和将结果写回内存的操作全部依赖于CPU中设计的逻辑来实现。
这种架构会增加CPU结构的复杂性和对CPU工艺的要求，但对于编译器的开发十分有利。
比如上面的例子，C程序中的a*=b就可以直接编译为一条乘法指令。
今天只有Intel及其兼容CPU还在使用CISC架构。

RISC架构要求软件来指定各个操作步骤。
上面的例子如果要在RISC架构上实现，将ADDRA, ADDRB中的数据读入寄存器，相乘和将结果写回内存的操作都必须由软件来实现，
比如：

MOV A, ADDRA;

MOV B, ADDRB;

MUL A, B;

STR ADDRA, A

这种架构可以降低CPU的复杂性以及允许在同样的工艺水平下生产出功能更强大的CPU，但对于编译器的设计有更高的要求。

巴特西

smaller programs should improve performance RISC(精简指令集计算机)和CISC(复杂指令集计算机)是当前CPU的两种架构区别示例

CPU体系架构

RISC与CISC

最新文章

热门文章

巴特西

smaller programs should improve performance RISC(精简指令集计算机)和CISC(复杂指令集计算机)是当前CPU的两种架构 区别示例

CPU体系架构

RISC与CISC

最新文章

热门文章

smaller programs should improve performance RISC(精简指令集计算机)和CISC(复杂指令集计算机)是当前CPU的两种架构区别示例