UVM基础之--------uvm

uvm_root 是uvm的顶层实例扮演了一个top-level and phase controller 的作用，对于component来说。该类不需要用户实例化，他是一个自动实例化了的类，用户直接通过uvm_top调用。任何component，只要没有指定其parent，那么他将作为top的一个child。top管理所有component的phase；

1. The UVM automatically creates a single instance of uvm_root that users can access via the global (uvm_pkg-scope) variable, uvm_top.

2. uvm_top实例的关键作用：

1. Implicit top-level（隐式的顶层） The uvm_top serves as an implicit top-level component. Any component whose parent is specified as NULL becomes a child of uvm_top. Thus, all UVM components in simulation are descendants of uvm_top.所有组建的parent被指定为NULL的，就会成为uvm_top的child，uvm_top是uvm组建树的顶层。

2. Phase control uvm_top manages the phasing for all components.

3. Search Use uvm_top to search for components based on their hierarchical name. See find and find_all.（使用uvm_top基于层次名搜索组件）

4. Report configuration Use uvm_top to globally configure report verbosity, log files, and actions. For example, uvm_top.set_report_verbosity_level_hier(UVM_FULL) would set full verbosity for all components in simulation.

5. Global reporter Because uvm_top is globally accessible (in uvm_pkg scope), UVM’s reporting mechanism is accessible from anywhere outside uvm_component, such as in modules and sequences. See uvm_report_error, uvm_report_warning, and other global methods.

1.属性

uvm_component top_levels[$];//各个top注册在这 i.e test，It includes the uvm_test_top component that is created by run_test as well as any other top level components that have been instantiated anywhere in the hierarchy.

bit enable_print_topology = 0;//如果被设置，在end_of_elaboration phase结束的时候打印拓扑结构

bit finish_on_completion = 1;//If set, then run_test will call $finish after all phases are executed.

time phase_timeout = `UVM_DEFAULT_TIMEOUT;

static local uvm_root m_inst;

bit m_phase_all_done;//所有阶段执行完毕

2. 主要的API方法：

1. virtual task run_test ( string test_name = "" )：//解析命令行的"+UVM_TESTNAME="，从工厂中取出uvm_test_top并构造一个实例，调用相应的实例。

1. Phases all components through all registered phases

2. If the optional test_name argument is provided, or if a command-line plusarg, +UVM_TESTNAME=TEST_NAME, is found, then the specified component is created just prior to phasing.

2. find/find_all:

1. function void uvm_root::find_all(string comp_match, ref uvm_component comps[$],

input uvm_component comp=null); //查找整个uvm_top，调用m_find_all_recurse实现

2.function uvm_component uvm_root::find (string comp_match);//调用uvm_root::find_all实现

3. uvm_root私有函数：

1. function uvm_root::new();//设置reporter, command_processor,调用report_header

1. 调用super.new("__top__",null)将uvm_root设置成树的顶层

2. 设置reporter，拿到command_processor，调用report_header

3. 调用m_check_verbosity通过命令行获取并设置verbosity

2. function uvm_root uvm_root::get();

1. 构成uvm_root的单态类

2. 调用了uvm_domain::get_common_domain()；m_inst.m_domain = uvm_domain::get_uvm_domain()即生成了两个domain 一个common 一个uvm_domain

3. task uvm_root::run_phase (uvm_phase phase);//该函数主要检查$time是否为0，如果不为0就报告错误，因为run必须从0时刻开始

4. function void uvm_root::m_do_dump_args();//如果命令行有+UVM_DUMP_CMDLINE_ARGS，就把命令行的所有参数输出

5. function void uvm_root::build_phase(uvm_phase phase);//调用一些内建函数完成对uvm仿真环境的配置：

super.build_phase(phase);

m_set_cl_msg_args();

m_do_verbosity_settings();//解析命令行输入+uvm_set_verbosity=，主要进行一些语法检查，如果发现问题就报错，并不对设置做处理

m_do_timeout_settings();//解析命令行的"+UVM_TIMEOUT="，并把该设置应用于uvm_top

m_do_factory_settings();//解析命令行的+(UVM_SET_INST_OVERRIDE|uvm_set_inst_override)=，调用m_process_inst_override或者调用m_process_type_override

m_do_config_settings();从命令行中获取+(UVM_SET_CONFIG_INT|uvm_set_config_int)=设置，并解析该设置，最后调用m_process_config记录这些设置到resource数据库里边

m_do_max_quit_settings();+UVM_MAX_QUIT_COUNT=解析命令行的这个选项，并把该选项的设置设置入全局的report_server

m_do_dump_args(); //如果命令行有+UVM_DUMP_CMDLINE_ARGS，就把命令行的所有参数输出

来自为知笔记(Wiz)

巴特西

UVM基础之--------uvm_root

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