model NVIC_REG6T_1024x32(resetb,margin,clk,en,we,addr,d,q)

 (

      bist_definition(

            clock     clk    high;

            chip_enable   en    low;

            write_enable   we   high;

            data_in      d(array=:;);

            data_out    q(array=:;);

            address      addr(array=:;);

           dont_touch  margin(array=:;)high;

           dont_touch   resetb low;

           tech = smic11;

           vendor = mentor;

           version="1.0";

           message= "synchrous single port sram";

           address_size = ;

           min_address = ;

           max_address = ;

           read_write_port(

                read_cycle(

                    change addr;

                    wait;

                    wait;

                    expect q;

                    wait;

                 )

                write_cycle(

                     change addr;

                     change d;

                     wait ;

                     assert we;

                     wait;

                     wait;

                   )

            )

       )

 )

 model NVIC_ROM_1024x32(resetb,margin,clk,en,addr,q)

 (

     bist_definition(

             clock  clk  high ;

             chip_enable en low;

             data_out      q(array=:;);

             address    addr(array=:;);

              dont_touch       margin high;

              dont_touch       resetb  low;

              tech = smic11;

              vendor = mentor;

              version = "1.0";

              message = "synchronous single port sram";

              address_size = ;

              min_address = ;

              max_address = ;

              data_size = ;

               read_port(

                    read_cycle(

                        change addr;

                        wait;

                        expect q;

                        wait;

                     )

                )

       )

 )